Resistive memory devices and related methods
First Claim
1. A memory device, comprising:
- an array of memory cells, each memory cell comprising a resistive memory element programmable between a high resistance state and a low resistance state;
a decoder electrically coupled to one or more word lines comprised in the array of memory cells, the decoder configured to decode an address input to select a word line of the one or more word lines comprised in the array of memory cells;
a binarizer electrically coupled to the array of memory cells and configured to receive a plurality of memory cell outputs from the array of memory cells and generate a plurality of binary weighted memory cell outputs in response to the decoder selecting a word line of the one or more word lines of the array of memory cells, wherein each binary weighted memory cell output corresponds with one memory cell;
a summer electrically coupled to the binarizer and configured to sum the binary weighted memory cell outputs into an analog signal; and
a quantizer electrically coupled to the summer and configured to convert the analog signal into a digital output.
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Accused Products
Abstract
A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors and which may include a magnetic tunnel junction. A decoder decodes input address information to select a row of the array. A binarizer coupled to the memory array assigns binary weights to outputs of the memory array output through bit lines coupled to the memory cells. A summer sums the binary weighted outputs, and a quantizer generates an output digital code corresponding to data stored in a plurality of memory cells during a prior program cycle. The outputs of the memory array may be currents or voltages. In implementations multiple arrays of memory cells may be utilized and their respective outputs combined to form higher bit outputs, such as eight bit, twelve bit, sixteen bit, and so forth.
56 Citations
20 Claims
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1. A memory device, comprising:
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an array of memory cells, each memory cell comprising a resistive memory element programmable between a high resistance state and a low resistance state; a decoder electrically coupled to one or more word lines comprised in the array of memory cells, the decoder configured to decode an address input to select a word line of the one or more word lines comprised in the array of memory cells; a binarizer electrically coupled to the array of memory cells and configured to receive a plurality of memory cell outputs from the array of memory cells and generate a plurality of binary weighted memory cell outputs in response to the decoder selecting a word line of the one or more word lines of the array of memory cells, wherein each binary weighted memory cell output corresponds with one memory cell; a summer electrically coupled to the binarizer and configured to sum the binary weighted memory cell outputs into an analog signal; and a quantizer electrically coupled to the summer and configured to convert the analog signal into a digital output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of using a memory device, comprising:
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decoding a word line address of an array of memory cells through a decoder and selecting the decoded word line, each memory cell comprising a resistive memory element programmable between a high resistance state and a low resistance state; applying a control voltage to clamp transistors coupled to memory cells of the selected word line; assigning binary weights to bit line currents to form binary weighted bit line currents; summing the binary weighted bit line currents to generate an analog output current; and quantizing the analog output current into a 4n bit digital code through a current quantizer, where n is a positive integer. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method of using a memory device, comprising:
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decoding a word line address of an array of memory cells through a decoder and selecting the decoded word line, each memory cell comprising a resistive memory element programmable between a high resistance state and a low resistance state; applying a current to memory cells of the selected word line; assigning binary weights to bit line voltages to form binary weighted bit line voltages; summing the binary weighted bit line voltages to generate an analog output voltage; and quantizing the analog output voltage into a (4+m)n bit digital code through a quantizer, wherein m is an integer and n is a positive integer. - View Dependent Claims (17, 18, 19, 20)
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Specification