CAM NAND with or function and full chip search capability

• US 8,773,909 B2
• Filed: 08/01/2013
• Issued: 07/08/2014
• Est. Priority Date: 11/09/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Li, Yan, Sprouse, Steven T.
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US13/957,219
• Publication Number:
  US 20140136763A1
• Time in Patent Office: 341 Days
• Field of Search: 36518501-18533
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor

Abstract

Various techniques for extending the capabilities of CAM NAND type memories are discussed. Multi-block or even full chip search operations can be performed. In addition to the inherent AND property of NAND strings, the memory array has an inherent OR property between NAND string from different blocks along the same bit line that can be exploited through multi-block CAM-type operations. To reduce data-dependent word line to word line effects, in multiple data dependent sensing operations, the sensing can be broken up into sub-operations that avoid data dependent values on adjacent word lines. To improve data protection, subsequent to writing a memory block with indices, the word lines are read back and compared bit-by-bit with their intended values and the results are accumulated to determine whether any of indices include error. A bloom filter can also be used as an initial check during data search operations in order to provide increased data protection.

Claims

1. A method of operating a memory system, the memory system including an array of non-volatile memory cells arranged into a NAND type of architecture, including a plurality NAND strings and a plurality word lines spanning the NAND strings, each of the word lines connected to a corresponding one of the memory cells thereof, the method comprising:

receiving a search data pattern;

splitting the search data pattern into a plurality of sub-patterns including at least first and second sub-patterns respectively corresponding to first and second sets of non-adjacent ones of the word lines;

performing a first determination comprising;

biasing the corresponding first set of the word lines according to the first sub-pattern; and

concurrently determining those of the NAND strings that conduct in response to the corresponding first set of the word lines biased according to the first sub-pattern being applied thereto;

performing a second determination comprising;

biasing the corresponding second set of the word lines according to the second sub-pattern; and

concurrently determining those of the NAND strings that conduct in response to the corresponding second set of the word lines biased according to the second sub-pattern being applied thereto; and

subsequently combining results of the first and second determinations to determine those of the NAND strings that conduct in response to the word lines biased according to the first and second sub-patterns being applied thereto.

2. The method of claim 1, wherein the array is formed of a plurality of blocks and the first and second sets of word lines are from different blocks.

3. The method of claim 1, wherein the array is formed of a plurality of blocks and the first and second sets of word lines are from the same block.

4. The method of claim 3, wherein the word lines of one of the first and second sets of word lines are even word lines and the other of the first and second sets of word lines are odd word lines.

5. The method of claim 1, wherein said biasings include setting those of the word lines of NAND strings not biased according to the corresponding sub-pattern to a pass value.

6. The method of claim 1, where each of the NAND strings is connected along a corresponding bit line having an associated plurality of latches, and wherein the first and second determinations include storing the result of the corresponding determining in a respective first and second one of the corresponding associated latches, and wherein said combining results of the first and second determinations is based on the results stored in the latches.

7. The method of claim 1, wherein each of the NAND string stores a corresponding data pattern and a copy of the corresponding data pattern.

8. The method of claim 1, wherein each of the NAND string stores a corresponding data pattern and an inverted copy of the corresponding data pattern.

9. The method of claim 8, wherein at least one of the sub-pattern does not include the word lines corresponding to both a first bit of the search data pattern and the first bit in inverted form for the search pattern.

10. The method of claim 1, further comprising:

receiving from a host device to which the memory system is connected a plurality of data patterns;

forming the plurality of data patterns into pages of data whereby, when written into the memory, the data patterns will lie along the NAND strings; and

writing the pages of data a page at a time, each page being written along on of the word lines, wherein the data pages are written to be non-sequentially order on the word lines.

11. The method of claim 10, wherein a first half of the data pages are written on odd ones of the word lines and a second half of data pages are written on even ones of the word lines.

12. The method of claim 10, wherein each of the pages of data are written in along two of the word lines.

13. The method of claim 10, wherein each of the pages of data are written in along a first of the word lines and, in inverted form, along a second of the word lines.

14. The method of claim 1, wherein the first and second sub-patterns correspond to first and second attributes of data sets stored along the NAND strings.

15. A method of operating a memory system, the memory system including a memory circuit having an array of non-volatile memory cells arranged into a plurality of blocks, each of the blocks including a first plurality NAND strings and a plurality word lines spanning the NAND strings, each of the word lines connected to a corresponding one of the memory cells thereof, where a first plurality of bit lines span the blocks with each of the blocks having one of the NAND strings thereof connected along a corresponding one of the bit lines, the method comprising:

storing a plurality of data patterns each along a bit line of the memory array, where each of the data patterns are stored in inverted and non-inverted forms along the same bit line, the bits of the non-inverted form of the data patterns being stored along a first set of word lines and the bits of the inverted form of the data patterns being stored along a second set of word lines;

receiving a search pattern; and

performing a determination of whether any of the stored data patterns match the search pattern, including;

applying the search pattern to the first set of word lines and applying the search pattern in inverted form to the second set of word lines, wherein the search pattern and inverted form of the search pattern are applied in a plurality of sensing operations in which a plurality of non-adjacent word lines for one or more blocks are concurrently biased to a data dependent voltage level based upon the search pattern.

16. The method of claim 15, wherein the first and second set of word lines belong to the same block of the memory array.

17. The method of claim 15, wherein the first and second set of word lines respective belong to first and second blocks of the memory array, where the first and second blocks are different.

18. The method of claim 15, wherein the data dependent bias voltages are margined high relative to the corresponding bias voltage levels used in a program verify operation.

19. The method of claim 15, wherein the bits of the data patterns are stored along the NAND strings in a non-consecutive order relative to their order as received at the memory system from a host device for one or both of the patterns in non-inverted and inverted form.

20. A method of operating a memory system, the memory system including a memory circuit having an array of non-volatile memory cells arranged into a plurality of blocks, each of the blocks including a first plurality NAND strings and a plurality word lines spanning the NAND strings, each of the word lines connected to a corresponding one of the memory cells thereof, where a first plurality of bit lines span the blocks with each of the blocks having one of the NAND strings thereof connected along a corresponding one of the bit lines, the method comprising:

storing a plurality of data patterns each along a bit line of the memory array, where each of the data patterns a first copy and a second copy are stored along the same bit line, the bits of the first copy being stored along a first set of word lines and the bits of the second copy being stored along a second set of word lines;

receiving a data search query; and

performing a search operation on the stored data patterns based upon the data search query, including;

concurrently biasing first and second word lines respectively from the first and second sets of word lines to a voltage level based upon the data search query, where the first and second word lines correspond to the same bit of the data patterns respectively from the first and second copies thereof.

21. The method of claim 20, wherein the first and second set of word lines belong to the same block of the memory array.

22. The method of claim 21, wherein the data dependent bias voltages are margined high relative to the corresponding bias voltage levels used in a program verify operation.

23. The method of claim 20, wherein the first and second set of word lines respective belong to first and second blocks of the memory array, where the first and second blocks are different.

24. The method of claim 23, wherein the data dependent bias voltages are margined low relative to the corresponding bias voltage levels used in a program verify operation.

25. The method of claim 20, wherein the bits of the data patterns are stored along the NAND strings in a non-consecutive order relative to their order as received at the memory system from a host device for one or both copies of the patterns.

26. The method of claim 20, where the data search query is range search for a data value.