Switching architecture with packet encapsulation
First Claim
1. A system for passing Time Division Multiplexed (TDM) traffic through a packet switch, comprisinga packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports, the packet switch routing FSDU packets within the packet switch based on header information within respective FSDU packets;
- a TDM encapsulation circuit coupled to a data flow of TDM data and having a circuit demultiplexer for processing an incoming data flow of TDM data to buffer data associated with different TDM circuits into different buffer locations,a timer for monitoring a frame boundary,a FSDU generator for generating an FSDU and filling the generated FSDU with data associated with a respective one of the TDM circuits and for generating the header information for allowing the packet switch to route the generated FSDU to a port associated with the respective one of the TDM circuits;
a bandwidth allocation process for allocating bandwidth for generated FSDU traffic to provide a predetermined latency period for routing FSDU traffic through the packet switch; and
a jitter buffer for receiving the generated FSDU traffic with the predetermined latency period, the jitter buffer further for reducing variable delays in the FSDU traffic, wherein the jitter buffer has a size selected as a function of a minimum and maximum latency of the FSDU traffic;
wherein the jitter buffer has a size selected to maintain jitter below 125 microseconds.
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Accused Products
Abstract
The invention includes, among other things, a system for passing TDM traffic through a packet switch. In one embodiment, the system includes a packet switch that has a plurality of data ports and is capable of routing FSDU packets between the plurality of data ports. A TDM encapsulation circuit process a TDM data flow that is incoming to the switch. A circuit demultiplexer processes the incoming data flow to buffer data associated with different TDM circuits into different buffer locations. A timer monitors the amount of time available to fill the FSDU, and when the time period reaches the frame boundary, an FSDU generator generates an FSDU that is filled with data associated with the TDM circuits. Header information is added for allowing the packet switch to route the generated FSDU to a port associated with the respective TDM circuit.
26 Citations
14 Claims
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1. A system for passing Time Division Multiplexed (TDM) traffic through a packet switch, comprising
a packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports, the packet switch routing FSDU packets within the packet switch based on header information within respective FSDU packets; -
a TDM encapsulation circuit coupled to a data flow of TDM data and having a circuit demultiplexer for processing an incoming data flow of TDM data to buffer data associated with different TDM circuits into different buffer locations, a timer for monitoring a frame boundary, a FSDU generator for generating an FSDU and filling the generated FSDU with data associated with a respective one of the TDM circuits and for generating the header information for allowing the packet switch to route the generated FSDU to a port associated with the respective one of the TDM circuits; a bandwidth allocation process for allocating bandwidth for generated FSDU traffic to provide a predetermined latency period for routing FSDU traffic through the packet switch; and a jitter buffer for receiving the generated FSDU traffic with the predetermined latency period, the jitter buffer further for reducing variable delays in the FSDU traffic, wherein the jitter buffer has a size selected as a function of a minimum and maximum latency of the FSDU traffic; wherein the jitter buffer has a size selected to maintain jitter below 125 microseconds. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A process for passing Time Division Multiplexed (TDM) traffic through a packet switch, comprising
providing a packet switch having a plurality of data ports and being capable of routing Fixed Size Data Unit (FSDU) packets between the plurality of data ports, the packet switch routing the FSDU packets within the packet switch based on header information within respective FSDU packets; -
identifying a TDM data flow, encapsulating the TDM data flow by sorting the TDM data flow into different respective buffer locations, generating an FSDU that can pass through the packet switch and filling the generated FSDU with data associated with a respective one of the TDM circuits, generating the header information for routing the generated FSDU to a port associated with the respective one of the TDM circuits, combining the generated FSDU with a flow of packet data being sent to the packet switch; allocating bandwidth for generated FSDU traffic to provide a predetermined latency period for routing FSDU traffic through the packet switch; receiving the FSDU traffic with the predetermined latency period by a jitter buffer, wherein the jitter buffer has a size selected as a function of a minimum and maximum latency of the FSDU traffic; and reducing variable delays in the FSDU traffic by the jitter buffer; wherein the time period is set to the TDM frame boundary period. - View Dependent Claims (11, 12, 13, 14)
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Specification