Single wire bus system
First Claim
1. A single wire bus architecture comprising:
- a single wire bus;
a master device coupled to the single wire bus;
at least one slave device coupled to the single wire bus;
a delay unit having two capacitors that are alternately charged by a fixed current so that a charging voltage on the capacitors is used to determine points where the single wire bus is activated and sampled; and
a communication protocol implemented over the single wire bus for communication between the master device and the at least one slave device;
wherein the communication protocol employs the use of a continuous clock signal and bi-directional data transmission within each clock cycle for communication between the master device and the at least one slave device;
wherein the bus is in a tri-state period during bi-directional data transmission in which one of the master device or the at least one slave device can pull down or leave the clock signal unchanged to signal a data value; and
wherein timing between the continuous clock signal and the bi-directional data is defined by leading and trailing edges of each clock cycle.
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Accused Products
Abstract
There is provided a single wire bus architecture comprising a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; a communication protocol implemented over the single wire bus and employed by the master device and the at least one slave device; wherein when one of the at least one slave devices wishes to communicate with the master device, the one of the at least one slave devices discharges the clock signal during a tri-state stage of the clock signal; and wherein the single wire bus transmits a clock signal, power and data between the master device and the one of the at least one slave device in communication with the master device.
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Citations
22 Claims
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1. A single wire bus architecture comprising:
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a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; a delay unit having two capacitors that are alternately charged by a fixed current so that a charging voltage on the capacitors is used to determine points where the single wire bus is activated and sampled; and a communication protocol implemented over the single wire bus for communication between the master device and the at least one slave device; wherein the communication protocol employs the use of a continuous clock signal and bi-directional data transmission within each clock cycle for communication between the master device and the at least one slave device; wherein the bus is in a tri-state period during bi-directional data transmission in which one of the master device or the at least one slave device can pull down or leave the clock signal unchanged to signal a data value; and wherein timing between the continuous clock signal and the bi-directional data is defined by leading and trailing edges of each clock cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A single wire bus architecture comprising:
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a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; and a delay unit having two capacitor s that are alternately charged by a fixed current so that a charging voltage on the capacitors is used to determine points where the single wire bus is activated and sampled, wherein the master device and the at least one slave device communicate by time-multiplexing a set of bus cycles, each of the bus cycles including a clock signal portion and a bi-directional data transmission portion for data transmission between the master device and the at least one slave device, wherein during said bi-directional data transmission portion the bus is in a tri-state period in which one of the master device or the at least one slave device can pull down or leave the clock signal unchanged to signal a data value; and
, wherein discharging of the clock signal by either the master device or the at least one slave device occurs after a particular time period and within each bus cycle. - View Dependent Claims (20, 21, 22)
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Specification