Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories

• US 8,775,717 B2
• Filed: 04/08/2008
• Issued: 07/08/2014
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Prins, Douglas A., Olbrich, Aaron K.
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US12/082,207
• Publication Number:
  US 20090172308A1
• Time in Patent Office: 2,282 Days
• Field of Search: 711/5, 711/140, 711/147, 711/169, 710/317
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a plurality of internal memories. The memories contain work lists for the processors. In one embodiment, the processors communicate by using the crossbar switch to place tasks on the work lists of other processors.

Claims

1. A flash memory controller for controlling a flash memory, comprising:

a plurality of processors each with a register, an ALU and an internal memory, the plurality of processors including;

a first set of processors; and

a second set of processors;

a plurality of random access memories, including;

a first set of random access memories in the plurality of random access memories including one or more data structures related to memory commands; and

a second set of random access memories in the plurality of random access memories each including a work queue for a corresponding processor of the plurality of processors;

a crossbar switch connecting the plurality of processors with the plurality of random access memories, the crossbar switch including;

a set of processor ports including one port for a respective processor and a set of memory ports including one port for a respective random access memory; and

an internal switching mechanism configured to connect any processor port with any memory port, but not configured to connect a processor port with another processor port or a memory port with another memory port;

wherein a processor in the first set of processors is configured to place a task for a processor in the second set of processors through the crossbar switch on a work queue associated with the processor in the second set of processors, the task placed on the work queue comprises a pointer to a data structure in the first set of random access memories.

2. The flash memory controller as in claim 1, further including:

an arbitrator that controls access to a crossbar switch memory port if more than one processor is seeking access to the crossbar switch memory port, the arbitrator controlling the crossbar switch internal switching mechanism to provide access to a processor that has won an arbitration.

3. The flash memory controller as in claim 1, wherein:

at least one of the random access memories in the first set of random access memories is a data structure that is formatted to store metadata but includes one or more fields that do not currently store valid metadata.

4. The flash memory controller as in claim 1, wherein:

at least one work queue is controlled by a set of registers, the set of registers including a first register storing information from which an empty work queue can be distinguished from a work queue that contains at least one task; and

the flash memory controller further includes a signal connected to a processor, the signal being controlled by the first register, the signal being triggered by a transition between an empty work queue and a work queue containing a task, the signal causing the processor connected to the signal to terminate a sleep mode.

5. The flash memory controller of claim 1, wherein:

the first set of processors and the second set of processors are configured to handle different stages of a pipelined execution of host storage commands.

6. A method of operating a flash storage controller to control a flash memory, the flash storage controller including a first and second processor, a crossbar switch connecting a plurality of processors with first and second random access memories, but not connecting a processor with another processor or a random access memory with another random access memory, the method comprising the following steps:

the first processor storing a first data structure in a processor memory internal to the first processor;

the first processor accessing a first crossbar switch port associated with the first random access memory;

the first processor copying the first data structure to the first random access memory;

the first processor accessing a second crossbar switch port associated with the second random access memory;

the first processor placing a pointer to the first data structure in a worklist stored in the second random access memory, the worklist corresponding to the second processor;

the second processor accessing the first crossbar switch port;

the second processor copying the first data structure from the first random access memory to a processor memory internal to the second processor; and

the second processor modifying the first data structure.

7. The method as in claim 6, further including:

the second processor populating fields of a second data structure, the second data structure located in the processor memory internal to the second processor; and

modifying the first data structure includes adding, to the first data structure, a pointer to the second data structure.

8. The method as in claim 7, wherein the first data structure includes a logical address;

and

the method further including;

placing a first physical flash address in a second data structure field, the first physical flash address being related to the logical address.

9. The method as in claim 8, further including:

the second processor populating fields of a third data structure, the third data structure located in the processor memory internal to the second processor; and

modifying the first data structure includes adding, to the first data structure, a pointer to the third data structure.

10. The method as in claim 9, further including:

placing a second physical flash address in a third data structure field, the second physical flash address being related to the logical address.

11. The method of claim 6, further comprising:

the second processor accessing data from a flash memory through a bus switch coupling the second processor and a buffer to the flash memory.

12. A flash memory controller for controlling a flash memory comprising:

a first processor and a second processor, a respective processor including a register, an ALU and an internal processor memory;

a first volatile memory containing a first worklist, the first worklist being associated with the first processor;

a second volatile memory containing a second worklist, the second worklist being associated with the second processor;

a third volatile memory containing a first data structure relating to a first host command;

a fourth volatile memory containing a second data structure relating to a second host command;

a crossbar switch connecting a plurality of processors with a plurality of random access memories, including;

a set of processor ports, a respective processor port in the set of processor ports connected to a processor, including a first processor port connected to the first processor and a second processor port connected to the second processor;

a set of memory ports, a respective memory port in the set of memory ports connected to a volatile memory, including a first memory port connected to the first volatile memory, a second memory port connected to the second volatile memory and a third memory port connected to the third volatile memory and a fourth memory port connected to the fourth volatile memory; and

internal circuitry connecting one of the processor ports to one of the memory ports, but not connecting a processor with another processor or a random access memory with another random access memory; and

a bus switch coupling the second processor and a buffer with the flash memory;

wherein the first processor is configure to place a pointer to the first data structure on the second worklist corresponding to the second processor.

13. The controller as in claim 12, wherein:

the first worklist contains first information related to the first host command; and

the second worklist contains second information related to the second host command.

14. The controller as in claim 13, wherein:

the first information constitutes a pointer to the first data structure; and

the second information constitutes a pointer to the second data structure.

15. The controller as in claim 14, wherein:

the first worklist includes a pointer to a third data structure, the third data structure relating to the second host command.

16. The controller as in claim 14, wherein:

the first and second data structures include a logical address, but do not include a physical address; and

the first processor internal processor memory includes a fourth data structure, the fourth data structure including a physical address.