Power management with dynamic frequency adjustments

• US 8,775,843 B2
• Filed: 02/04/2013
• Issued: 07/08/2014
• Est. Priority Date: 02/11/2008
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Frid, Aleksandr, Sriram, Parthasarathy
• Primary Examiner(s): DU, THUAN N
• Application Number:
  US13/758,936
• Publication Number:
  US 20130212417A1
• Time in Patent Office: 519 Days
• Field of Search: 713/310, 713/322, 713/323
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.

Claims

1. A system comprising:

a device operable for executing a task; and

a processor coupled to said device, wherein said processor specifies a value for a frequency for a clock signal used by said device and thereafter said processor is placed in a reduced power mode;

wherein said device is operable to perform said task after said processor is placed in said reduced power mode until a triggering event causes said device to send an interrupt to said processor;

wherein in response to said interrupt said processor awakens to dynamically adjust said frequency of said clock signal so that a metric satisfies a first condition.

2. The system of claim 1 wherein said interrupt is sent based on a measure of buffer capacity of a buffer associated with said device.

3. The system of claim 1 wherein said interrupt is sent if a measure of workload is predicted to change during execution of said task.

4. The system of claim 1 wherein said metric is based on an amount of time said device is idle while said task is executed.

5. The system of claim 4 wherein said processor increases said value of said frequency of said clock signal if said metric is less than a corresponding threshold value and decreases said value for said frequency for said clock signal if said metric is more than a corresponding threshold value.

6. The system of claim 4 wherein said amount of time is measured over a sample interval, wherein said sample interval is extended in length if said value for said frequency of said clock signal is reduced.

7. The system of claim 1 wherein said value for said frequency of said clock signal is specified according to a type of said task.

8. The system of claim 1 wherein reduced power mode comprises power gating said processor.

9. A method comprising:

operating a processor in a first power mode;

in response to a selection of a device to perform a task and a selection of a value for a frequency for a clock used by said device, entering a reduced power mode at said processor, wherein said frequency of said clock remains set to said value until a triggering event occurs;

awakening said processor in response to an interrupt generated by said device so that said processor can dynamically adjust said value for said frequency of said clock.

10. The method of claim 9 further comprising:

monitoring a measure of buffer capacity associated with said device; and

sending said interrupt if said measure is less than a threshold.

11. The method of claim 9 further comprising sending said interrupt if an increase in workload associated with performing said task is predicted.

12. The method of claim 9 further comprising:

with said processor in said first operating mode subsequent to said awakening, monitoring a metric that corresponds to an amount of time said device is idle while performing said task;

increasing said value of said frequency for said clock if said metric is less than a corresponding threshold value; and

decreasing said value of said frequency for said clock if said metric is greater than a corresponding threshold value.

13. The method of claim 9 wherein said selection of said value for said frequency for said clock depends on a type of said task.

14. The method of claim 9 further comprising power gating said processor in said reduced power mode.

15. A system comprising:

a processor; and

a device coupled to said processor, wherein said processor specifies a value for a baseline clock frequency for said device and then enters a reduced power mode, wherein said device executes tasks using said value for said baseline clock frequency and awakens said processor from said reduced power mode if said value for said baseline clock frequency is to be changed.

16. The system of claim 15 wherein said value for said baseline clock frequency is to be changed in response to a triggering event selected from the group consisting of:

buffer capacity of said device does not satisfy a threshold value;

workload of said device is predicted to change; and

amount of time said device is idle does not satisfy a threshold value.

17. The system of claim 15 wherein said device sends an interrupt to said processor to awaken said processor.

18. The system of claim 15 wherein, after said processor awakens, said processor adjusts said value for said baseline clock frequency and then returns to said reduced power mode.

19. The system of claim 15 wherein a respective value for said baseline frequency is predefined for each of said tasks, wherein said value for said baseline frequency is looked up by said processor knowing said tasks to be performed.

20. The system of claim 15 further comprising a second device coupled to said processor, wherein said processor specifies a second value for a second baseline clock frequency for said second device before entering said reduced power mode, wherein said second device executes tasks using said second value for said second baseline clock frequency and awakens said processor from said reduced power mode if said second value for said second baseline clock frequency is to be changed.