Method for producing a structure element and semiconductor component comprising a structure element

• US 8,778,751 B2
• Filed: 09/19/2011
• Issued: 07/15/2014
• Est. Priority Date: 09/21/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Poelzl, Martin
• Primary Examiner(s): AU, BAC H
• Application Number:
  US13/235,550
• Publication Number:
  US 20120068260A1
• Time in Patent Office: 1,030 Days
• Field of Search: 438/270, 438/221, 438/361, 438/435, 438/437
• US Class Current: 438/221
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle α in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body.

Claims

1. A method for producing a structure element on a surface of a semiconductor body, the method comprising:

providing a semiconductor body having a surface;

producing a cutout at the surface, the cutout extending from surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface, the cutout having a base, at least one sidewall and an edge at the intersection of the surface and the at least one sidewall;

producing a first auxiliary layer on the surface of the semiconductor body and in the cutout so that the first auxiliary layer forms a well above the cutout, the well having a well base and at least one well sidewall which forms an angle α

in the range of 20°

to 80°

with respect to the surface of the semiconductor body, the at least one well sidewall extending above the surface and across the edge such that a defined distance of the surface is covered by the at least one well sidewall;

producing a second auxiliary layer within the well at the well base and at the at least one well sidewall, the first auxiliary layer and the second auxiliary layer forming a common surface at an identical surface level, the second auxiliary layer comprising a different material than the first auxiliary layer; and

selectively removing regions of the first auxiliary layer which are not covered by the second auxiliary layer.

2. A method according to claim 1, wherein the first auxiliary layer is produced by an HDP process.

3. A method according to claim 2, wherein before the first auxiliary layer is produced, a continuous protective layer is produced on the surface of the semiconductor body and in the cutout.

4. A method according to claim 1, wherein the second auxiliary layer is produced by depositing the different material in the well.

5. A method according to claim 4, wherein the second auxiliary layer completely fills the well.

6. A method according to claim 5, wherein the common surface of the first and second auxiliary layers is produced by a CMP method.

7. A method according to claim 1, wherein the second auxiliary layer is removed from the well after the regions of the first auxiliary layer which are not covered by the second auxiliary layer are selectively removed.

8. A method according to claim 7, wherein the second auxiliary layer is removed during the production of a trench into the semiconductor body.

9. A method according to claim 8, wherein the trench has at least one trench sidewall which, proceeding from an edge of the first auxiliary layer, extends into the semiconductor body.

10. A method according to claim 1, wherein the at least one well sidewall extends across the edge such that the first auxiliary layer covers the surface by a distance of 50 nm to 150 nm.

11. A method according to claim 1, wherein the first auxiliary layer has an edge which, proceeding from an edge of the well, extends in the direction of the surface of the semiconductor body.

12. A method according to claim 11, wherein the edge of the first auxiliary layer is rounded at the well edge such that the edge of the first auxiliary layer at the well edge between the second auxiliary layer and the edge forms an angle α

of less than 90°

.