Method of making an insulated gate semiconductor device having a shield electrode structure and structure therefor

• US 8,778,764 B2
• Filed: 07/16/2012
• Issued: 07/15/2014
• Est. Priority Date: 07/16/2012
• Status: Active Grant

• Current Assignee: ON Semiconductor Corporation, Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Hossain, Zia
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): FOX, BRANDON C
• Application Number:
  US13/550,156
• Publication Number:
  US 20140015039A1
• Time in Patent Office: 729 Days
• Field of Search: 257/139, 257/330, 438/270
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In one embodiment, a semiconductor device includes a multi-portion shield electrode structure formed in a drift region. The shield electrode includes a wide portion formed in proximity to a channel side of the drift region, and a narrow portion formed deeper in the drift region. The narrow portion is separated from the drift region by a thicker dielectric region, and the wide portion is separated from the drift region by a thinner dielectric region. That portion of the drift region in proximity to the wide portion can have a higher dopant concentration than other portions of the drift region.

Claims

1. A method for making an insulated gate semiconductor device having a shield electrode structure comprising:

providing a region of semiconductor material having a major surface;

forming a first trench extending from the major surface into the region of semiconductor material;

forming a dielectric structure along surfaces of the first trench, the dielectric structure comprising a first dielectric layer along surfaces of the first trench and a second dielectric layer overlying the first dielectric layer;

removing portions of the first and second dielectric layers along a lower surface of the first trench;

forming a second trench extending from the first trench into the region of semiconductor material;

forming a third dielectric layer along surfaces of the second trench, wherein the third dielectric layer is thicker than the dielectric structure;

forming a shield electrode within the second trench along the third dielectric layer and within a portion of the first trench along a portion of the dielectric structure, wherein the shield electrode has a wide portion adjacent the dielectric structure and a narrow portion adjacent the third dielectric layer;

removing a portion of the second dielectric layer after forming the shield electrode, wherein another portion of the second dielectric layer remains between the wide portion and the first dielectric layer;

forming an inter-electrode dielectric layer overlying the wide portion;

forming a gate electrode overlying the inter-electrode dielectric layer; and

forming a body region within the region of semiconductor material, wherein the body region and the first trench are adjacent.

2. The method of claim 1 further comprising forming a doped region within the region of semiconductor material in proximity to the wide portion but not in proximity to at least a portion of the narrow portion, wherein the body region is between the major surface and the doped region, and wherein the doped region has a higher dopant concentration than that of the region of semiconductor material.

3. The method of claim 1, wherein forming the second dielectric layer includes forming a nitride layer.

4. A method for forming a semiconductor device comprising:

providing a region of semiconductor material having a semiconductor layer of a first conductivity type and having a major surface;

forming a trench structure;

forming a shield electrode within the trench structure having a first portion and a second portion, wherein the first portion is wider than the second portion, and wherein the first portion is separated at least in part from the semiconductor layer by a first dielectric layer, and wherein the second portion is separated from the semiconductor layer by a second dielectric layer that is thicker than the first dielectric layer;

forming a doped region of the first conductivity type in the semiconductor layer, wherein the doped region is in proximity to the first portion of the shield electrode but not in proximity to at least a portion of the second portion of the shield electrode, and wherein the doped region has a higher dopant concentration than that of the semiconductor layer;

forming an insulated gate electrode in the trench structure; and

forming a body region of a second conductivity type in the semiconductor layer extending from the major surface, wherein the body region and the trench structure are adjacent, wherein the body region is between the major surface and the doped region.

5. The method of claim 4, wherein forming the doped region in proximity to the first portion but not adjoining any part of the second portion.

6. The method of claim 4 further comprising forming a dielectric liner between the first dielectric layer and the first portion.

7. The method of claim 6, wherein forming the dielectric liner comprises forming a nitride liner.

8. A method for forming a semiconductor device comprising:

providing a region of semiconductor material having a semiconductor layer of a first conductivity type and having a major surface;

forming a trench structure extending from the major surface at least into the semiconductor layer;

forming a shield electrode within the trench structure having a first portion and a second portion, wherein the first portion is wider than the second portion, and wherein the first portion is separated at least in part from the semiconductor layer by a first dielectric layer, and wherein the second portion is separated from the semiconductor layer by a second dielectric layer that is thicker than the first dielectric layer;

forming a dielectric liner between the first dielectric layer and the first portion of the shield electrode;

forming an insulated gate electrode in the trench structure;

forming a body region of a second conductivity type in the semiconductor layer extending from the major surface, wherein the body region and the trench structure are adjacent; and

forming a source region of the first conductivity type in spaced relationship with the body region.

9. The method of claim 8 further comprising forming a doped region of the first conductivity type in the semiconductor layer in proximity to the first portion of the shield electrode, wherein the body region is between the major surface and the doped region, and wherein the doped region has a higher dopant concentration than that of the semiconductor layer.

10. The method of claim 9, wherein forming the doped region includes forming the doped region in proximity to the first portion of the shield electrode but not in proximity to at least a portion of the second portion of the shield electrode.

11. The method of claim 8, wherein forming the dielectric liner comprises forming a nitride liner.