Method for defining semiconductor devices

• US 8,778,780 B1
• Filed: 10/11/2006
• Issued: 07/15/2014
• Est. Priority Date: 10/13/2005
• Status: Active Grant

• Current Assignee: Semileds Optoelectronics Company Limited (SemiLEDs Inc)
• Original Assignee: Semileds Optoelectronics Company Limited (SemiLEDs Inc)
• Inventors: Fan, Feng-Hsu, Doan, Trung-Tri, Chu, Chen-Fu, Cheng, Hao-Chun
• Primary Examiner(s): KIM, SU C
• Application Number:
  US11/548,633
• Time in Patent Office: 2,834 Days
• Field of Search: 438/22, 438/26, 438/33, 438/34, 438/42, 438/460, 438/463, 438/68, 438/113, 438/462, 257/14, 257/79, 257/E21.347, 257/E21.599
• US Class Current: 438/463
• CPC Class Codes: H01L 2933/0075 relating to heat extraction or cooling elements
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01S 5/00 Semiconductor lasers superluminescent diodes H01L33/00
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/32341 blue laser based on GaN or GaP

Abstract

Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.

Claims

1. A method comprising:

providing a wafer assembly comprising a substrate having a device side and an opposing back side, and a plurality of semiconductor layers on the device side of the substrate;

applying a laser to cut through the semiconductor layers and into the device side of the substrate, without cutting completely through the substrate to form a plurality of substrate trenches and walls, and to define a plurality of semiconductor devices on the substrate, with the substrate trenches and the walls configured such that at least two substrate trenches and at least one wall are formed between each adjacent semiconductor device; and

removing the substrate from the semiconductor layers after the applying the laser step by laser irradiation of the back side of the substrate with a laser energy, with the walls reducing the laser energy on the semiconductor devices and preventing damage during the laser irradiation.

2. The method of claim 1 wherein the applying the laser step forms a plurality of walls between each adjacent semiconductor device.

3. The method of claim 1 wherein the applying the laser step forms two substrate trenches and one wall between each adjacent semiconductor device.

4. The method of claim 1 wherein the substrate trenches have a depth of from 0.001 μ

m to 300 μ

m.

5. The method of claim 1 wherein the applying the laser step forms four substrate trenches and three walls between each adjacent semiconductor device.

6. The method of claim 1 wherein the applying the laser step forms the substrate trenches with a width of 0.1 μ

m to 300 μ

m.

7. The method of claim 1 wherein the laser has a wavelength of 266 nm or 355 nm.

8. The method of claim 1 wherein the semiconductor layers comprise an n-doped layer on the substrate and a p-doped layer on the n-doped layer and a width of a substrate trench at the p-doped layer is wider than a width of the substrate trench at the n-doped layer.

9. The method of claim 1 further comprising using wet etching or dry etching after the applying the laser step to further define the semiconductor devices.

10. The method of claim 1 further comprising using wet etching or dry etching before the applying the laser step.

11. The method of claim 1 wherein the applying the laser step is performed using an oxygen-containing environment.

12. The method of claim 1 further comprising applying a protective coating to a surface of the wafer assembly before the applying the laser step.

13. The method of claim 12 wherein the protective coating comprises a polymer.

14. The method of claim 12 further comprising:

removing the protective coating after the applying the laser step; and

cleaning the semiconductor devices.

15. The method of claim 1 further comprising cleaning the semiconductor devices in a liquid.

16. The method of claim 15 wherein the liquid comprises an acid or a base with or without an oxidizer.

17. The method of claim 15 wherein the liquid comprises H2SO4:

H202, HNO3, HNO3;

HCl, NH40H;

H202, KOH;

H2O2, or H3PO4.

18. A method comprising:

providing a wafer assembly comprising a substrate having a device side and an opposing back side, an n-doped layer on the device side of the substrate, a multiple quantum well (MQW) layer on the n-doped layer, and a p-doped layer on the (MQW) layer;

cutting through the p-doped layer, the (MQW) layer, and the n-doped layers and into the device side of the substrate with a laser without cutting completely through the substrate to form a plurality of substrate trenches and walls, and define a plurality of vertical light-emitting diode (VLED) devices on the substrate, with the substrate trenches and the walls configured such that at least two substrate trenches and at least one wall are formed between each adjacent (VLED) device; and

removing the substrate from the semiconductor layers after the cutting step by laser irradiation of the back side of the substrate with a laser energy, with the walls reducing the laser energy on the (VLED) devices and preventing damage during the laser irradiation.

19. The method of claim 18 wherein the cutting step forms a plurality of walls between each adjacent (VLED) device.

20. The method of claim 18 wherein the cutting step forms four substrate trenches and three walls between each adjacent (VLED) device.

21. The method of claim 18 wherein a width of the substrate trenches at the p-doped layer is wider than the width of the substrate trenches at the n-doped layer.

22. The method of claim 18 further comprising applying a protective coating to a surface of the wafer assembly before the cutting step.

23. The method of claim 22 further comprising:

removing the protective coating after the cutting step; and

cleaning the (VLED) devices.

24. The method of claim 18 further comprising cleaning the (VLED) devices using a solution.