Resistance change memory and method of manufacturing the same

• US 8,779,410 B2
• Filed: 01/23/2012
• Issued: 07/15/2014
• Est. Priority Date: 06/29/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sato, Motoyuki, Asao, Yoshiaki, Obara, Takashi, Nakazawa, Takashi
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Anya, Igwe U
• Application Number:
  US13/355,692
• Publication Number:
  US 20130001506A1
• Time in Patent Office: 904 Days
• Field of Search: 257/5, 438/382, 438/3
• US Class Current: 257/5
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

According to one embodiment, a resistance change memory includes resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements. The elements are provided in a lattice pattern having a constant pitch. A thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers. The vias are provided in the holes respectively.

Claims

1. A method of manufacturing a resistance change memory, the memory comprising resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements, wherein the elements are provided in a lattice pattern having a constant pitch, a thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls has at least a value for contacting the sidewall insulating layers to each other to form holes between the sidewall insulating layers, and the vias are provided in the holes respectively, and each of the resistance change elements is a magnetoresistive element including magnetic layers,

the method comprising:

forming the elements;

forming an insulating material covering the elements;

forming the holes in a self-alignment when the sidewall insulating layers is formed by etching back the insulating material; and

forming the vias in the holes respectively.

2. The method of claim 1,

wherein the etching back is executed to expose the elements to form upper electrodes at the same time of forming the vias, and each of the upper electrodes is connected to one of the vias and one of the elements.

3. The memory of claim 1,

wherein the vias are selected from a group of tungsten, titanium, titanium nitride, copper, tantalum, and tantalum nitride.

4. The method of claim 1,

wherein the magnetoresistive element comprises an under layer, a magnetoresistive layer on the under layer, a shift adjustment layer on the magnetoresistive layer, and a mask layer on the shift adjustment layer.

5. The method of claim 1,

wherein a planar shape of the magnetoresistive element is a round shape, a quadrangular shape, or an elliptic shape.

6. The method of claim 1,

wherein a planar shape of each of the vias is a star shape, a quadrangular shape, or an elliptic shape.

7. The method of claim 1,

wherein the sidewall insulating layer covers the sidewall of the magnetoresistive element.

8. The method of claim 1,

wherein the sidewall insulating layer is formed by an atomic layer deposition (ALD) method.

9. The method of claim 1,

wherein the vias are provided in a lattice pattern having a constant pitch.

10. The method of claim 1, further comprising an FET is connected between a magnetoresistive element and a via adjacent to each other in the first direction.

11. The method of claim 1, further comprising an upper electrode is connected between a magnetoresistive element and a via adjacent to each other in the second direction.

12. The method of claim 11, further comprising bit lines extending in the first direction,

wherein each of the bit lines is connected alternatively to upper electrodes arranged in the first direction.

13. A resistance change memory comprising:

resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements, wherein the elements are provided in a lattice pattern having a constant pitch, a thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls has at least a value for contacting the sidewall insulating layers to each other to form holes between the sidewall insulating layers, and the vias are provided in the holes respectively, and each of the resistance change elements is a magnetoresistive element including magnetic layers.

14. The memory of claim 13,

wherein each of the sidewall insulating layers includes a first layer comprising a first material and a second layer comprising a second material different from the first material.

15. The memory of claim 14,

wherein the first layer contacts with one of the elements and prevents an oxidation thereof, and the second layer has a dielectric constant lower than that of the first layer.

16. The memory of claim 14,

wherein the first and second materials are selected from a group of silicon nitride, boron nitride, aluminium nitride, silicon oxide, aluminium oxide, magnesium oxide, hafnium oxide, lanthanum oxide, zirconium oxide and yttrium oxide.

17. The memory of claim 13, further comprising:

a first FET connected between a first element and a first via adjacent to each other in the first direction among the elements and the vias;

a second FET connected between a second element and a second via adjacent to each other in the first direction among the elements and the vias;

a first word line connected to a gate of the first FET, and extending to the second direction;

a second word line connected to a gate of the second FET, and extending to the second direction;

a first upper electrode connected to the first element;

a second upper electrode connected to the first via and the second element;

a third upper electrode connected to the second via;

a first bit line connected to the first and third upper electrodes, and extending the first direction; and

a second bit line connected to the second upper electrode, and extending the first direction,

wherein the first and second elements are adjacent to each other in the constant pitch.

18. The memory of claim 13,

wherein the value for contacting the sidewall insulating layers to each other is

(√

{square root over (2)}×

F)−

Sm/2,

where 4 F is the constant pitch, and Sm is a size of each of the elements.

19. The memory of claim 13,

wherein a planer shape of each of the elements is a round shape, and a planer shape of each of the vias is a star shape.