Semiconductor device

• US 8,779,420 B2
• Filed: 11/23/2012
• Issued: 07/15/2014
• Est. Priority Date: 11/28/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US13/684,290
• Publication Number:
  US 20130082256A1
• Time in Patent Office: 599 Days
• Field of Search: 257/43, 257/E29.296, 438/104
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/2206 Amorphous materials
• CPC Class Codes: H01L 29/221 including two or more compounds , e.g. alloys H01L29/2206 takes precedence
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a first oxide semiconductor layer over the gate electrode layer with the gate insulating layer interposed therebetween;

a second oxide semiconductor layer on the first oxide semiconductor layer;

a source electrode layer and a drain electrode layer over and electrically connected to the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises indium and zinc,

wherein the second oxide semiconductor layer comprises indium and zinc,

wherein the second oxide semiconductor layer comprises a first crystalline region,

wherein the first crystalline region has a c-axis aligned in a direction substantially perpendicular to a surface of the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a second crystalline region, and

wherein the second crystalline region has a c-axis aligned in a direction substantially perpendicular to a surface of the first oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×

10¹⁹/cm³.

3. The semiconductor device according to claim 1, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises more zinc than indium.

4. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer comprises gallium.

5. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer comprises gallium.

6. The semiconductor device according to claim 1, wherein the first crystalline region comprises a stacked structure of a first layer comprising indium and a second layer comprising zinc and not comprising indium.

7. The semiconductor device according to claim 1, wherein the gate electrode layer comprises copper.

8. The semiconductor device according to claim 1, further comprising an interlayer insulating layer over the source electrode layer and the drain electrode layer.

9. The semiconductor device according to claim 1,

wherein the second oxide semiconductor layer comprises a first region and a second region,

wherein the first region overlaps with the source electrode layer or the drain electrode layer,

wherein the second region overlaps with neither the source electrode layer nor the drain electrode layer, and

wherein the second region is thinner than the first region.

10. The semiconductor device according to claim 1, wherein a carrier density in at least one of the first oxide semiconductor layer and the second oxide semiconductor layer is less than 1×

10¹²/cm³.

11. The semiconductor device according to claim 1, wherein a sum of thicknesses of the first oxide semiconductor layer and the second oxide semiconductor layer is larger than or equal to 3 nm and smaller than or equal to 50 nm.

12. The semiconductor device according to claim 1, wherein the c-axis is aligned in a direction within ±

10°

from a perpendicular to the surface of the second oxide semiconductor layer.

13. The semiconductor device according to claim 1, wherein a distance between the source electrode layer and the drain electrode layer is longer than or equal to 10 nm and shorter than or equal to 1000 nm.

14. The semiconductor device according to claim 1, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises an intrinsic oxide semiconductor.

15. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise a material including the same main component.

16. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise materials including different main components from each other.

17. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer have the same crystal structure.

18. A semiconductor device comprising:

a first oxide semiconductor layer;

a second oxide semiconductor layer on the first oxide semiconductor layer;

a source electrode layer and a drain electrode layer over and electrically connected to the second oxide semiconductor layer;

a gate insulating layer over the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer;

a gate electrode layer over the second oxide semiconductor layer with the gate insulating layer interposed therebetween,

wherein the first oxide semiconductor layer comprises indium and zinc,

wherein the second oxide semiconductor layer comprises indium and zinc,

wherein the second oxide semiconductor layer comprises a first crystalline region,

wherein the first crystalline region has a c-axis aligned in a direction substantially perpendicular to a surface of the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a second crystalline region, and

wherein the second crystalline region has a c-axis aligned in a direction substantially perpendicular to a surface of the first oxide semiconductor layer.

19. The semiconductor device according to claim 18, wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×

10¹⁹/cm³.

20. The semiconductor device according to claim 18, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises more zinc than indium.

21. The semiconductor device according to claim 18, wherein the first oxide semiconductor layer comprises gallium.

22. The semiconductor device according to claim 18, wherein the second oxide semiconductor layer comprises gallium.

23. The semiconductor device according to claim 18, wherein the first crystalline region comprises a stacked structure of a first layer comprising indium and a second layer comprising zinc and not comprising indium.

24. The semiconductor device according to claim 18, wherein the gate electrode layer comprises copper.

25. The semiconductor device according to claim 18, further comprising an interlayer insulating layer over the source electrode layer and the drain electrode layer.

26. The semiconductor device according to claim 18,

wherein the second oxide semiconductor layer comprises a first region and a second region,

wherein the first region overlaps with the source electrode layer or the drain electrode layer,

wherein the second region overlaps with neither the source electrode layer nor the drain electrode layer, and

wherein the second region is thinner than the first region.

27. The semiconductor device according to claim 18, wherein the c-axis is aligned in a direction within ±

10°

from a perpendicular to the surface of the second oxide semiconductor layer.

28. The semiconductor device according to claim 18, wherein a distance between the source electrode layer and the drain electrode layer is longer than or equal to 10 nm and shorter than or equal to 1000 nm.

29. The semiconductor device according to claim 18, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises an intrinsic oxide semiconductor.

30. The semiconductor device according to claim 18, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise a material including the same main component.

31. The semiconductor device according to claim 18, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise materials including different main components from each other.

32. The semiconductor device according to claim 18, wherein the first oxide semiconductor layer and the second oxide semiconductor layer have the same crystal structure.

33. A semiconductor device comprising:

a first gate electrode layer;

a first gate insulating layer over the first gate electrode layer;

a first oxide semiconductor layer over the first gate electrode layer with the first gate insulating layer interposed therebetween;

a second oxide semiconductor layer on the first oxide semiconductor layer;

a source electrode layer and a drain electrode layer over and electrically connected to the second oxide semiconductor layer,

a second gate insulating layer over the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer,

a second gate electrode layer over the first gate electrode layer with the second gate insulating layer interposed therebetween,

wherein the first oxide semiconductor layer comprises indium and zinc,

wherein the second oxide semiconductor layer comprises indium and zinc,

wherein the second oxide semiconductor layer comprises a first crystalline region, and

wherein the first crystalline region has a c-axis aligned in a direction substantially perpendicular to a surface of the second oxide semiconductor layer.

34. The semiconductor device according to claim 33, wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×

10¹⁹/cm³.

35. The semiconductor device according to claim 33, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises more zinc than indium.

36. The semiconductor device according to claim 33, wherein the first crystalline region comprises a polycrystal.

37. The semiconductor device according to claim 33, wherein the first oxide semiconductor layer comprises gallium.

38. The semiconductor device according to claim 33, wherein the second oxide semiconductor layer comprises gallium.

39. The semiconductor device according to claim 33, wherein the first crystalline region comprises a stacked structure of a first layer comprising indium and a second layer comprising zinc and not comprising indium.

40. The semiconductor device according to claim 33, wherein each of the first gate electrode layer and the second gate electrode layer comprises copper.

41. The semiconductor device according to claim 33,

wherein the first oxide semiconductor layer comprises a second crystalline region, and

wherein the second crystalline region has a c-axis aligned in a direction substantially perpendicular to a surface of the first oxide semiconductor layer.

42. The semiconductor device according to claim 33, wherein the second gate electrode layer comprises an indium tin oxide.

43. The semiconductor device according to claim 33, wherein the second gate electrode layer comprises an indium zinc oxide.

44. The semiconductor device according to claim 33, further comprising an interlayer insulating layer over the source electrode layer and the drain electrode layer.

45. The semiconductor device according to claim 33,

wherein the second oxide semiconductor layer comprises a first region and a second region,

wherein the first region overlaps with the source electrode layer or the drain electrode layer,

wherein the second region overlaps with neither the source electrode layer nor the drain electrode layer, and

wherein the second region is thinner than the first region.

46. The semiconductor device according to claim 33, wherein the c-axis is aligned in a direction within ±

10°

from a perpendicular to the surface of the second oxide semiconductor layer.

47. The semiconductor device according to claim 33, wherein a distance between the source electrode layer and the drain electrode layer is longer than or equal to 10 nm and shorter than or equal to 1000 nm.

48. The semiconductor device according to claim 33, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises an intrinsic oxide semiconductor.

49. The semiconductor device according to claim 33, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise a material including the same main component.

50. The semiconductor device according to claim 33, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise materials including different main components from each other.

51. The semiconductor device according to claim 33, wherein the first oxide semiconductor layer and the second oxide semiconductor layer have the same crystal structure.

52. A semiconductor device comprising:

a gate electrode layer;

a first oxide semiconductor layer adjacent to the gate electrode layer with a gate insulating layer interposed therebetween;

a second oxide semiconductor layer on the first oxide semiconductor layer;

a source electrode layer and a drain electrode layer over and electrically connected to the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises indium and zinc,

wherein the second oxide semiconductor layer comprises indium and zinc,

wherein the second oxide semiconductor layer comprises a crystalline region,

wherein the crystalline region has a c-axis aligned in a direction substantially perpendicular to a surface of the second oxide semiconductor layer,

wherein the crystalline region comprises a layer parallel with an a-axis and a b-axis of the crystalline region, and

wherein the layer comprises indium.

53. The semiconductor device according to claim 52, wherein a hydrogen concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than or equal to 5×

10¹⁹/cm³.

54. The semiconductor device according to claim 52, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises more zinc than indium.

55. The semiconductor device according to claim 52, wherein the crystalline region comprises a polycrystal.

56. The semiconductor device according to claim 52, wherein the first oxide semiconductor layer comprises gallium.

57. The semiconductor device according to claim 52, wherein the second oxide semiconductor layer comprises gallium.

58. The semiconductor device according to claim 52, wherein the gate electrode layer is provided over the second oxide semiconductor layer.

59. The semiconductor device according to claim 52, wherein the first oxide semiconductor layer is provided over the gate electrode layer.

60. The semiconductor device according to claim 52, wherein the c-axis is aligned in a direction within ±

10°

from a perpendicular to the surface of the second oxide semiconductor layer.

61. The semiconductor device according to claim 52, wherein a distance between the source electrode layer and the drain electrode layer is longer than or equal to 10 nm and shorter than or equal to 1000 nm.

62. The semiconductor device according to claim 52, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises an intrinsic oxide semiconductor.

63. The semiconductor device according to claim 52, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise a material including the same main component.

64. The semiconductor device according to claim 52, wherein the first oxide semiconductor layer and the second oxide semiconductor layer comprise materials including different main components from each other.

65. The semiconductor device according to claim 52, wherein the first oxide semiconductor layer and the second oxide semiconductor layer have the same crystal structure.