Stress-alleviation layer for LED structures

• US 8,779,445 B2
• Filed: 07/24/2008
• Issued: 07/15/2014
• Est. Priority Date: 07/02/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Lin, Hung-Ta, Chen, Ding-Yuan, Chiou, Wen-Chih, Yu, Chia-Lin
• Primary Examiner(s): WRIGHT, TUCKER J
• Application Number:
  US12/179,160
• Publication Number:
  US 20100001257A1
• Time in Patent Office: 2,182 Days
• Field of Search: 257/13, 257/88, 257/E33.055
• US Class Current: 257/88
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating

Abstract

A light emitting diodes (LEDs) is presented. The LED includes a stress-alleviation layer on a substrate. Open regions and stress-alleviation layer regions are formed on the substrate. Epitaxial layers are disposed on the substrate, at least in the open regions therein, thereby forming an LED structure. The substrate is diced through at least a first portion of the stress-alleviation regions, thereby forming the plurality of LEDs.

Claims

1. A semiconductor structure, the structure comprising:

a dice comprising;

a substrate;

a non-crystalline stress-alleviation layer on the substrate;

open regions and a first stress-alleviation region on the substrate, the first stress-alleviation region being a part of the non-crystalline stress-alleviation layer and forming a ring-like structure along the periphery of the dice, the first stress-alleviation region surrounding all of the open regions on the dice, and the first stress-alleviation region not contacting another part of the non-crystalline stress-alleviation layer; and

epitaxial layers on the substrate, at least in the open regions, forming light emitting diode (LED) structures therein, the LED structures having bottom surfaces proximate the substrate and top surfaces distal the substrate, the non-crystalline stress-alleviation layer having a top surface substantially coplanar with the top surfaces of the LED structures.

2. The structure of claim 1, wherein the substrate is selected from the group consisting of Si, sapphire, SiC and GaN.

3. The structure of claim 1, wherein the non-crystalline stress-alleviation layer is selected from the group consisting of SiO₂, SiN, III-Nitrides, or combinations thereof.

4. The structure of claim 1, wherein the epitaxial layers comprise at least one selective epitaxy layer.

5. The structure of claim 1 further comprising:

a precursor underlying the epitaxial layers.

6. The structure of claim 5, wherein the epitaxial layers comprise an at least one non-selective epitaxial layer.

7. The structure of claim 1, wherein the non-crystalline stress-alleviation layer is interposed between the substrate and an epitaxial layer.

8. The structure of claim 1, wherein the non-crystalline stress-alleviation layer is interposed between two epitaxial layers.

9. The structure of claim 1, further comprising a second stress-alleviation region on the substrate, the second stress-alleviation region being a part of the non-crystalline stress-alleviation layer and comprising at least one stress-alleviation island.

10. The structure of claim 1 further comprising:

a reflectivity layer added to the LED structures.

11. A semiconductor structure, the structure comprising:

a substrate having a major surface;

a plurality of non-crystalline, non-continuous stress-alleviation regions formed on the substrate, the plurality of stress-alleviation regions having bottom surfaces proximate the substrate and top surfaces distal the substrate; and

a plurality of light emitting diode (LED) structures formed on the substrate, wherein at least two of the plurality of LED structures comprise a stack of layers having substantially coterminous sidewalls, each of the substantially coterminous sidewalls contacting an at least one stress-alleviation region and extending from the substrate to the top surface of the at least one stress-alleviation region.

12. The semiconductor structure of claim 11, wherein a first portion of the plurality of non-crystalline, non-continuous stress-alleviation regions comprises a stress-alleviation layer on the substrate, and wherein a second portion of the plurality of non-crystalline, non-continuous stress-alleviation regions comprises regions open to the substrate.

13. The semiconductor structure of claim 11, wherein the plurality of LED structures border a plurality of stress-alleviation regions.

14. The semiconductor structure of claim 11, wherein a portion of the plurality of LED structures includes a stress-alleviation island, wherein the stress-alleviation island is comprised of a stress-alleviation region within an LED structure.

15. The semiconductor structure of claim 11, wherein the stack of layers comprises a top-side contact layer, the top-side contact layer having a surface substantially coplanar with the top surface of the at least one stress-alleviation layer.

16. A light emitting diode (LED) comprising:

a substrate;

stress-alleviation regions, at least one stress-alleviation region comprising a non-crystalline region, surrounded on all sides by an LED structure and physically separated from any other stress-alleviation region;

the LED structure comprising;

a buffer layer disposed on the substrate;

a quantum-well layer; and

a top-side contact, wherein a first contact epitaxial layer is interposed between the buffer layer and the quantum-well layer, and wherein a second contact epitaxial layer is interposed between the quantum-well layer and the top-side contact, and wherein an at least one of the stress-alleviation regions borders the LED structure.

17. The LED of claim 16, wherein an at least one of the stress-alleviation regions forms a ring-like structure surrounding a periphery of the substrate.

18. The LED of claim 16, wherein the stress-alleviation regions are disposed between the substrate and an epitaxial layer.

19. The LED of claim 16, wherein the stress-alleviation regions are disposed between two epitaxial layers.

20. The LED of claim 16, wherein the stress-alleviation regions have a thickness between about 0.1-5.0 μ

m.

21. The LED of claim 16 further comprising:

a reflectivity layer added to the LED structure.