Light source unit

• US 8,779,460 B2
• Filed: 08/16/2012
• Issued: 07/15/2014
• Est. Priority Date: 11/19/1997
• Status: Expired due to Fees

• Current Assignee: Epistar Corporation (Ennostar, Inc.)
• Original Assignee: Epistar Corporation (Ennostar, Inc.)
• Inventors: Salam, Hassan P. A.
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US13/587,279
• Publication Number:
  US 20120305980A1
• Time in Patent Office: 698 Days
• Field of Search: 257/94, 257/99, 257/E33.062
• US Class Current: 257/99
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/64 Heat extraction or cooling elements

Abstract

An embodiment discloses a light source unit including a first terminal, a first semiconductor layer supporting the first terminal, a second semiconductor layer surrounding the first terminal, and a second terminal electrically connected to the second semiconductor layer and not surrounding the first terminal.

Claims

1. A light source unit, comprising:

one or more first conductors;

a first terminal having one or more portions configured to contact the one or more first conductors;

a first semiconductor layer supporting the first terminal and the one or more first conductors;

a second semiconductor layer arranged on the first semiconductor layer to expose the first terminal and the one or more first conductors, and substantially surrounding the first terminal except the one or more portions; and

a second terminal electrically connected to the second semiconductor layer and not surrounding the first terminal.

2. The light source unit of claim 1, further comprising one or more trenches passing through the second semiconductor layer and exposing the first semiconductor layer.

3. The light source unit of claim 2, wherein the one or more first conductors are formed in the one or more trenches.

4. The light source unit of claim 1, further comprising one or more second conductors electrically connected to the second terminal and formed on the second semiconductor layer.

5. The light source unit of claim 4, wherein the one or more second conductors are arranged around the first terminal.

6. The light source unit of claim 4, wherein the one or more second conductors are arranged around the one or more first conductors.

7. The light source unit of claim 4, wherein the one or more second conductors are arranged in a symmetric pattern.

8. The light source unit of claim 1, further comprising a substrate having a diagonal line on which at least one of the first terminal and the second terminal is substantially arranged.

9. The light source unit of claim 1, wherein the one or more first conductors are arranged in a symmetric pattern.

10. The light source unit of claim 1, wherein the one or more first conductors have at least one conductor oriented towards the second terminal.

11. A chip, comprising:

a substrate having a diagonal line, a first corner on one end of the diagonal line, and a second corner on another end of the diagonal line;

a first terminal arranged on the first corner and having one or more portions;

a first semiconductor layer between the substrate and the first terminal;

a second semiconductor layer arranged on the first semiconductor layer and substantially surrounding the first terminal; and

a second terminal arranged on the second corner and not surrounding the first terminal.

12. The chip of claim 11, further comprising one or more first conductors arranged on the first semiconductor layer and connected to the one or more portions.

13. The chip of claim 12, wherein the second semiconductor layer are arranged to substantially surround the first terminal except the one or more portions.

14. The chip of claim 12, wherein the one or more first conductors have at least one conductor oriented towards the second terminal.

15. The chip of claim 12, wherein the one or more first conductors are arranged in a symmetric pattern.

16. The chip of claim 12, further comprising one or more trenches passing through the second semiconductor layer and exposing the first semiconductor layer.

17. The chip of claim 16, wherein the one or more first conductors are arranged in the one or more trenches.

18. The chip of claim 11, further comprising one or more second conductors electrically connected to the second terminal and formed on the second semiconductor.

19. The chip of claim 18, wherein the one or more second conductors are arranged in a symmetric pattern.

20. The chip of claim 11, further comprising a conductor electrically connected to the first terminal.