Semiconductor memory device

• US 8,779,488 B2
• Filed: 04/10/2012
• Issued: 07/15/2014
• Est. Priority Date: 04/15/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko
• Primary Examiner(s): Pham, Long
• Application Number:
  US13/443,027
• Publication Number:
  US 20120261734A1
• Time in Patent Office: 826 Days
• Field of Search: 257/296, 257/E27.084, 257/67, 257/71
• US Class Current: 257/296
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/86 having horizontal extensions
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring.

Claims

1. A semiconductor memory device comprising:

a first transistor;

a second transistor;

a third transistor comprising an oxide semiconductor film; and

a capacitor comprising;

a conductive film facing side surfaces of one of a source electrode and a drain electrode of the third transistor; and

a first insulating film between the conductive film and the one of the source electrode and the drain electrode of the third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, and

wherein the one of the source electrode and the drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor.

2. The semiconductor memory device according to claim 1,

wherein the oxide semiconductor film is in contact with at least a top surface of the source electrode of the third transistor and a top surface of the drain electrode of the third transistor,

wherein the third transistor further comprises a gate insulating film over the oxide semiconductor film, and

wherein the first insulating film is formed over the gate insulating film.

3. The semiconductor memory device according to claim 1,

wherein the conductive film and one of the source electrode and the drain electrode of the third transistor are configured to serve as a pair of capacitor electrodes, and

wherein at least the first insulating film is configured to serve as a dielectric film of the capacitor.

4. The semiconductor memory device according to claim 1, wherein the third transistor further comprises a second insulating film between the source electrode of the third transistor and the drain electrode of the third transistor.

5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device further comprises:

a bit line;

a word line; and

a source line,

wherein the other of the source and the drain of the first transistor is electrically connected to the bit line,

wherein a gate electrode of the third transistor is electrically connected to the word line, and

wherein a gate electrode of the second transistor and the other of the source and the drain of the second transistor are electrically connected to the source line.

6. The semiconductor memory device according to claim 1, wherein a thickness of the drain electrode of the third transistor is set to 1 to 4 times of a width of the drain electrode of the third transistor.

7. The semiconductor memory device according to claim 1, wherein the conductive film is grounded.

8. The semiconductor memory device according to claim 2, wherein the gate insulating film is configured to release oxygen by heat treatment.

9. The semiconductor memory device according to claim 2, wherein an oxygen diffusion coefficient of the first insulating film is smaller than an oxygen diffusion coefficient of the gate insulating film at temperatures higher than or equal to 250°

C. and lower than or equal to 450°

C.

10. The semiconductor memory device according to claim 2,

wherein the first insulating film is an aluminum oxide film, and

wherein the gate insulating film is a silicon oxide film or a silicon oxynitride film.

21. The semiconductor memory device according to claim 1, wherein the conductive film faces three side surfaces of the one of the source electrode and the drain electrode of the third transistor.

11. A semiconductor memory device comprising:

a first transistor;

a second transistor;

a third transistor comprising an oxide semiconductor film; and

a capacitor comprising;

a conductive film; and

a first insulating film between the conductive film and at least one of a source electrode and a drain electrode of the third transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein one of the source electrode and the drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor,

wherein the conductive film has a net shape when seen from the above, and

wherein the third transistor is provided in a mesh formed by the conductive film.

12. The semiconductor memory device according to claim 11,

wherein the oxide semiconductor film is in contact with at least a top surface of the source electrode of the third transistor and a top surface of the drain electrode of the third transistor,

wherein the third transistor further comprises a gate insulating film over the oxide semiconductor film, and

wherein the first insulating film is formed over the gate insulating film.

13. The semiconductor memory device according to claim 11,

wherein the conductive film and one of the source electrode and the drain electrode of the third transistor are configured to serve as a pair of capacitor electrodes, and

wherein at least the first insulating film is configured to serve as a dielectric film of the capacitor.

14. The semiconductor memory device according to claim 11, wherein the third transistor further comprises a second insulating film between the source electrode of the third transistor and the drain electrode of the third transistor.

15. The semiconductor memory device according to claim 11, wherein the semiconductor memory device further comprises:

a bit line;

a word line; and

a source line,

wherein the other of the source and the drain of the first transistor is electrically connected to the bit line,

wherein a gate electrode of the third transistor is electrically connected to the word line, and

wherein a gate electrode of the second transistor and the other of the source and the drain of the second transistor are electrically connected to the source line.

16. The semiconductor memory device according to claim 11, wherein a thickness of the drain electrode of the third transistor is set to 1 to 4 times of a width of the drain electrode of the third transistor.

17. The semiconductor memory device according to claim 11, wherein the conductive film is grounded.

18. The semiconductor memory device according to claim 12, wherein the gate insulating film is configured to release oxygen by heat treatment.

19. The semiconductor memory device according to claim 12, wherein an oxygen diffusion coefficient of the first insulating film is smaller than an oxygen diffusion coefficient of the gate insulating film at temperatures higher than or equal to 250°

C. and lower than or equal to 450°

C.

20. The semiconductor memory device according to claim 12,

wherein the first insulating film is an aluminum oxide film, and

wherein the gate insulating film is a silicon oxide film or a silicon oxynitride film.