Insulated gate semiconductor device

• US 8,779,507 B2
• Filed: 03/30/2012
• Issued: 07/15/2014
• Est. Priority Date: 03/31/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Miyata, Takuji, Takenaka, Kazumasa
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Lau, Christine C
• Application Number:
  US13/435,833
• Publication Number:
  US 20120248531A1
• Time in Patent Office: 837 Days
• Field of Search: 257/330, 257/331, 257/333, 257/334, 257/E29.052, 257/E29.121, 257/E29.131, 257/E29.136, 257/E29.201, 257/E29.257, 257/332, 438/270, 438/271, 438/272, 438/589
• US Class Current: 257/331
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A gate lead wiring and an electrical conductor connecting the gate lead wiring to a protective diode are arranged in a straight line without bending along one and the same side of the chip. A first gate electrode layer extending on the gate lead wiring and the electrical conductor, which connects them to the protective diode, has one bent portion or no bent portion. Further, the protective diode is arranged adjacent to the electrical conductor or the gate lead wiring, and a portion of the protective diode is arranged in close proximity to a gate pad portion.

Claims

1. An insulated gate semiconductor device comprising:

a first semiconductor layer of a first general conductivity type;

a channel layer of a second general conductivity type disposed on the first semiconductor layer;

a plurality of first trenches extending in a first direction in the plan view of the semiconductor device, the first trenches penetrating through the channel layer and reaching the first semiconductor layer;

a plurality of second trenches extending in a second direction in the plan view, each of the second trenches connecting a corresponding pair of first trenches in the plan view;

a first insulating film provided on inner walls of the first trenches and the second trenches;

a gate electrode disposed in the first trenches and the second trenches;

a second insulating film covering the gate electrode;

a source region of the first general conductivity type formed in a surface portion of the channel layer, the source region extending in the second direction in the plan view; and

a body region of the second general conductivity type formed in a surface portion of the channel layer so as to be in contact with the source region and a corresponding first trench;

wherein two of the first trenches and two of the second trenches define a cell which makes transistor operation possible, and

the cell comprises two body regions of the second general conductivity type formed in a surface portion of the channel layer.

2. The insulated gate semiconductor device of claim 1, wherein the source region is adjacent the second trench in the plan view.

3. The insulated gate semiconductor device of claim 1, further comprising a third trench connecting a terminal portion of a first trench and a terminal portion of another first trench that is next to the first trench.

4. The insulated gate semiconductor device of claim 3, wherein the body region extends to surround the third trench in the plan view.

5. The insulated gate semiconductor device of claim 1, further comprising a gate lead wiring provided in a straight line along one side of the first semiconductor layer in the plan view.

6. The insulated gate semiconductor device of claim 5, further comprising a gate metal layer extending along and connected to the gate lead wiring.

7. The insulated gate semiconductor device of claim 1, wherein the second trenches are connected to corresponding first trenches so as to form a T-shape in the plan view.

8. An insulated gate semiconductor device comprising:

a first semiconductor layer of a first general conductivity type;

a channel layer of a second general conductivity type disposed on the first semiconductor layer;

a plurality of first trenches extending in a first direction in the plan view of the semiconductor device, the first trenches penetrating through the channel layer and reaching the first semiconductor layer;

a plurality of second trenches extending in a second direction in the plan view, each of the second trenches connecting a corresponding pair of first trenches in the plan view;

a first insulating film provided on inner walls of the first trenches and the second trenches;

a gate electrode disposed in the first trenches and the second trenches;

a second insulating film covering the gate electrode; and

a source region of the first general conductivity type formed in a surface portion of the channel layer, the source region extending in the second direction in the plan view,

wherein two of the first trenches and two of the second trenches define a cell which makes transistor operation possible, and

the cell comprises two body regions of the second general conductivity type formed in a surface portion of the channel layer.

9. The insulated gate semiconductor device of claim 8, wherein the source region is adjacent a corresponding second trench in the plan view.

10. The insulated gate semiconductor device of claim 8, further comprising a third trench connecting a terminal portion of a first trench and a terminal portion of another first trench that is next to the first trench.

11. The insulated gate semiconductor device of claim 8, wherein the body regions are in contact with the source region.

12. The insulated gate semiconductor device of claim 10, wherein the body regions extend to surround the third trench in the plan view.

13. The insulated gate semiconductor device of claim 8, further comprising a gate lead wiring provided in a straight line along one side of the first semiconductor layer in the plan view.

14. The insulated gate semiconductor device of claim 13, further comprising a gate metal layer extending along and connected to the gate lead wiring.

15. The insulated gate semiconductor device of claim 8, wherein the second trenches are connected to corresponding first trenches so as to form a T-shape in the plan view.

16. An insulated gate semiconductor device comprising:

a first semiconductor layer of a first general conductivity type;

a channel layer of a second general conductivity type disposed on the first semiconductor layer;

a plurality of first trenches extending in a first direction in the plan view of the semiconductor device, the first trenches penetrating through the channel layer and reaching the first semiconductor layer;

a plurality of second trenches extending in a second direction in the plan view, each of the second trenches connecting a corresponding pair of first trenches in the plan view;

a first insulating film provided on inner walls of the first trenches and the second trenches;

a gate electrode disposed in the first trenches and the second trenches;

a second insulating film covering the gate electrode; and

a source region of the first general conductivity type formed in a surface portion of the channel layer, the source region extending in the second direction in the plan view,

wherein two of the first trenches and two of the second trenches define a cell which makes transistor operation possible, and

the cell comprises two body regions of the second general conductivity type formed in a surface portion of the channel layer, wherein the body regions are in contact with the source region.

17. The insulated gate semiconductor device of claim 16, wherein the source region is adjacent a corresponding second trench in the plan view.

18. The insulated gate semiconductor device of claim 16, further comprising a third trench connecting a terminal portion of a first trench and a terminal portion of another first trench that is next to the first trench.

19. The insulated gate semiconductor device of claim 18, wherein the body regions extend to surround the third trench in the plan view.

20. The insulated gate semiconductor device of claim 16, further comprising a gate lead wiring provided in a straight line along one side of the first semiconductor layer in the plan view.