On-chip heat spreader

• US 8,779,572 B2
• Filed: 11/05/2013
• Issued: 07/15/2014
• Est. Priority Date: 01/26/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chuan-Yi, Hao, Ching-Chen, Chou, Chen Cheng, Lin, Sheng-Yuan
• Primary Examiner(s): Clark, S. V.
• Assistant Examiner(s): SODERHOLM, KRISTA Z
• Application Number:
  US14/071,937
• Publication Number:
  US 20140054761A1
• Time in Patent Office: 252 Days
• Field of Search: 257/686, 257/E23.101, 257/675, 257/635, 257/637, 257/706, 257/707, 257/784, 257/774, 257/777, 438/418, 438/127, 438/124, 438/102, 438/106, 438/73, 438/122, 438/612, 438/667, 438/672, 438/675
• US Class Current: 257/686
• CPC Class Codes: H01L 21/4814 Conductive parts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05616 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/06131 : being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/06519 : including bonding areas providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/08145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/055 : the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/34 : Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/42 : Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Claims

1. A device comprising:

a semiconductor substrate having at least one active device in the semiconductor substrate;

a conductive interconnect feature in a first dielectric layer on a first surface of the semiconductor substrate, the conductive interconnect feature being coupled to the at least one active device;

a second dielectric layer over the first dielectric layer;

a third dielectric layer over the second dielectric layer;

a first bonding pad in the third dielectric layer, the first bonding pad being electrically coupled to the conductive interconnect feature; and

a first heat dissipating structure on the second dielectric layer, the first heat dissipating structure being electrically isolated from the first bonding pad and comprising a first major axis extending toward to an outer edge of the first surface, wherein the first heat dissipating structure has a bottom surface coplanar with a bottom surface of the first bonding pad.

2. The device of claim 1, wherein the first heat dissipating structure comprises a material selected from the group consisting essentially of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), gold (Au), silver (Ag), a copper-tin alloy, a gold-tin alloy, an indium-gold alloy, a lead-tin alloy, and combinations thereof.

3. The device of claim 1 further comprising:

a first through substrate via (TSV) extending through the semiconductor substrate;

a fourth dielectric layer on a second surface of the semiconductor substrate, the second surface being opposite the first surface;

a second bonding pad on the fourth dielectric layer; and

a second heat dissipating structure on the fourth dielectric layer, the second heat dissipating structure being electrically isolated from the second bonding pad and the first TSV.

4. The device of claim 3 further comprising a third bonding pad in the third dielectric layer, the second and third bonding pads being electrically coupled to the first TSV.

5. The device of claim 3, wherein the first TSV is coupled to the at least one active device.

6. The device of claim 3, wherein the first and second heat dissipating structures extend to an edge of the semiconductor substrate, respectively.

7. The device of claim 3 further comprising:

a second TSV extending through the semiconductor substrate;

a fourth bonding pad in the third dielectric layer, the fourth bonding pad being coupled to a first end of the second TSV; and

a fifth bonding pad on the fourth dielectric layer, the fifth bonding pad being coupled to a second end of the second TSV.

8. The device of claim 1, wherein the first heat dissipating structure further comprises a second major axis extending toward an outer edge of the semiconductor substrate, the second major axis being perpendicular to the first major axis.

9. A semiconductor device comprising:

a first semiconductor die comprising;

a first bonding pad on a first dielectric layer on a front-side surface of the semiconductor die;

a first through-substrate via (TSV) extending through the first semiconductor die, the TSV having a first end surface coplanar with the front-side surface of the first semiconductor die; and

a first heat spreader on the first dielectric layer, the first heat spreader being insulated from the first TSV and the first bonding pad and having at least one major axis extending along the front-side surface, the first heat spreader having a bottom surface coplanar with the first end surface of the first TSV.

10. The semiconductor device of claim 9, wherein the first semiconductor die comprises one or more active devices, the first TSV being electrically coupled to at least one of the one or more active devices.

11. The semiconductor device of claim 10, wherein the TSV is electrically coupled to the first bonding pad.

12. The semiconductor device of claim 10 further comprising:

a second semiconductor die attached to the first semiconductor die, the second semiconductor die comprising;

a second bonding pad on a second dielectric layer on a front-side surface of the second semiconductor die, wherein the second bonding pad is electrically connected to the first bonding pad; and

a second heat spreader on the second dielectric layer, the second heat spreader being insulated from the second bonding pad and the first bonding pad, and the second heat spreader physically contacting the first heat spreader.

13. The semiconductor device of claim 12, wherein each of the first and second heat spreaders extend to an edge of the semiconductor device.

14. The semiconductor device of claim 12, wherein the second semiconductor die comprises a second TSV extending through the second semiconductor die, the second bonding die being coupled to the second TSV and the first bonding pad being coupled to the first TSV.

15. The semiconductor device of claim 9, wherein the first semiconductor die comprises a third bonding pad on a third dielectric layer on a back-side surface, the third bonding pad being coupled to the first TSV.

16. The semiconductor device of claim 15 further comprising a third heat spreader on the third dielectric layer, the third heat spreader being insulated from the third bonding pad and the first TSV.

17. A method of forming a semiconductor device, the method comprising:

forming a first semiconductor die comprising;

forming a first through substrate via (TSV) through the first semiconductor die, the first TSV having a first end surface coplanar with a front-side surface of the first semiconductor die;

forming a first bonding pad on the front-side surface, the first bonding pad being electrically coupled to the first TSV; and

forming a first heat spreader on the front-side surface, the first heat spreader being insulated from the first TSV and the first bonding pad and having at least one major axis extending along the front-side surface, the first heat spreader having a bottom surface coplanar with the first end surface of the first TSV.

18. The method of claim 17, wherein the first semiconductor die comprises one or more active devices, and wherein the first TSV is electrically coupled to at least one of the one or more active devices.

19. The method of claim 17 further comprising:

forming a second semiconductor die comprising;

forming a second bonding pad on a front-side surface of the second semiconductor die, wherein the second bonding pad is electrically connected to the first bonding pad; and

forming a second heat spreader on the front-side surface of the second semiconductor die, the second heat spreader being insulated from the second bonding pad; and

attaching the first semiconductor die to the second semiconductor die, the first and second bonding pads being electrically coupled and the first and second heat spreaders being physically coupled.

20. The method of claim 19, wherein the forming the second semiconductor die further comprises:

forming a second TSV extending through the second semiconductor die, the second bonding pad being electrically coupled to the second TSV.