Mutual capacitance sensing using a self-capacitance sensing device
First Claim
1. A capacitance-sensing circuit comprising:
- an input node coupled to a capacitance sense pin coupled to a first electrode of a sense array, wherein the input node is a single signal path of a sensing channel of the capacitive-sensing circuit;
a transmit (TX) signal generation circuit to generate a TX signal to drive a second electrode of the sense array;
logic circuitry coupled to the TX signal generation circuit, wherein the logic circuitry is configured to selectively couple a first capacitor to the single signal path and a second capacitor to the single signal path timed with the TX signal, wherein the first capacitor and the second capacitor are coupled to ground; and
an analog-to-digital converter (ADC) coupled to receive a receive (RX) signal from the input node and to convert the RX signal into a digital value, wherein the digital value represents a mutual capacitance between the first electrode and the second electrode, wherein the ADC comprises a comparator comprising a first input coupled to the single signal path and a second input coupled to a voltage reference (Vref), wherein a direct electrical connection is formed on the single signal path between the capacitance sense pin and the first input of the comparator, wherein the logic circuitry is configured to selectively couple the first capacitor and the second capacitor to the single signal path in a non-overlapping manner and timed to capture the RX signal from a first edge of the TX signal and to capture the RX signal from a second edge of the TX signal.
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Accused Products
Abstract
Apparatuses and methods of mutual-capacitance sensing with a capacitance-sensing circuit, such as a self-capacitance sensing device (CSD). One apparatus includes an input node coupled to a capacitance sense pin to couple to a first electrode of a sense array, a transmit (TX) signal generation circuit to generate a TX signal to drive a second electrode of the sense array, logic circuitry coupled to the TX signal generation circuit and the input node. The logic circuitry is configured to selectively couple a first capacitor to the input node and a second capacitor to the input node timed with the TX signal. The apparatus further includes an analog-to-digital converter (ADC) coupled to receive a receive (RX) signal from the input node and to convert the RX signal into a digital value, the digital value representing a mutual capacitance between the first electrode and the second electrode.
38 Citations
16 Claims
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1. A capacitance-sensing circuit comprising:
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an input node coupled to a capacitance sense pin coupled to a first electrode of a sense array, wherein the input node is a single signal path of a sensing channel of the capacitive-sensing circuit; a transmit (TX) signal generation circuit to generate a TX signal to drive a second electrode of the sense array; logic circuitry coupled to the TX signal generation circuit, wherein the logic circuitry is configured to selectively couple a first capacitor to the single signal path and a second capacitor to the single signal path timed with the TX signal, wherein the first capacitor and the second capacitor are coupled to ground; and an analog-to-digital converter (ADC) coupled to receive a receive (RX) signal from the input node and to convert the RX signal into a digital value, wherein the digital value represents a mutual capacitance between the first electrode and the second electrode, wherein the ADC comprises a comparator comprising a first input coupled to the single signal path and a second input coupled to a voltage reference (Vref), wherein a direct electrical connection is formed on the single signal path between the capacitance sense pin and the first input of the comparator, wherein the logic circuitry is configured to selectively couple the first capacitor and the second capacitor to the single signal path in a non-overlapping manner and timed to capture the RX signal from a first edge of the TX signal and to capture the RX signal from a second edge of the TX signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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driving a first electrode of a sense array with a transmit (TX) signal by a capacitance-sensing circuit; receiving a receive (RX) signal on a capacitance sense pin coupled to a second electrode of the sense array, wherein the capacitance sense pin is coupled to an input node of a multiplexer (MUX) bus of the capacitance-sensing circuit, wherein the input node is a single signal path of a sensing channel of the capacitive-sensing circuit; selectively coupling a first capacitor to the single signal path and a second capacitor to the single signal path timed with the TX signal, wherein the first capacitor and the second capacitor are coupled to ground; and converting the RX signal into a digital value by an analog-to-digital converter (ADC) of the capacitance-sensing circuit, wherein the ADC comprises a comparator comprising a first input coupled to the single signal path and a second input coupled to a voltage reference (Vref), wherein the digital value represents a mutual capacitance between the first electrode and the second electrode, wherein a direct electrical connection is formed on the single signal path between the capacitance sense pin and the first input of the comparator, wherein the selectively coupling comprises; selectively coupling the first capacitor to the single signal path in time to capture the RX signal from a first edge of the TX signal; and selectively coupling the second capacitor to the single signal path in a non-overlapping manner and in time to capture the RX signal from a second edge of the TX signal. - View Dependent Claims (11, 12, 13, 14)
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15. An apparatus comprising:
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a first external capacitor coupled to ground; a second external capacitor coupled to ground; a processing device comprising; an analog-to-digital converter (ADC) comprising a comparator comprising a first input coupled to a single signal path and a second input coupled to a voltage reference (Vref); a multiplexer bus coupled to single signal path of the ADC; and logic circuitry configured to selectively couple the first external capacitor and the second external capacitor to the single signal path in a non-overlapping manner; wherein the processing device is configured to drive a first electrode of a sense array with a transmit (TX) signal and to measure a receive (RX) signal on the multiplexer bus and convert the RX signal to a digital value by the ADC, wherein the multiplexer bus is coupled to a capacitance sense pin of the processing device, and wherein a direct electrical connection is formed on the single signal path between the capacitance sense pin and the first input of the comparator; a first switch coupled between the single signal path and the first capacitor, wherein the logic circuitry is configured to selectively activate the first switch to selectively couple the first capacitor to the single signal path; and a second switch coupled between the single signal path and the second capacitor, wherein the logic circuitry is configured to selectively activate the second switch to selectively couple the second capacitor to the single signal path, wherein the logic circuitry is to activate the first switch and the second switch in the non-overlapping manner. - View Dependent Claims (16)
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Specification