Transmitter output impedance calibration for output rise and fall time equalization and edge rate control

• US 8,779,819 B1
• Filed: 04/30/2013
• Issued: 07/15/2014
• Est. Priority Date: 04/30/2012
• Status: Active Grant

• Current Assignee: Microsemi Solutions (U.S.), Inc. (Microchip Technology Incorporated)
• Original Assignee: PMC Sierra US Inc (Microchip Technology Incorporated)
• Inventors: Venditti, Michael Ben
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/873,639
• Time in Patent Office: 441 Days
• Field of Search: 327/170
• US Class Current: 327/170
• CPC Class Codes: H03K 5/086 generated by feedback

Abstract

A method and apparatus to independently adjust the output rise and fall time of a transmitter for the purposes of improving high-speed signaling characteristics and reducing electromagnetic interference (EMI). Also described is an apparatus to provide a high-speed edge-rate control feature. The disclosed method and apparatus for rise and fall time equalization has a closed-loop calibration system that includes an actuation apparatus within the transmitter driver, a sensing means at the output of the transmitter to measure the degree of rise/fall time imbalance, and a calibration state machine operating on the sensor output to devise correction control inputs to the actuator in the transmitter driver to correct the rise/fall time imbalance. Also described is how the actuation apparatus within the transmitter driver can further be used to provide an open-loop edge-rate control feature for the transmitter.

Claims

1. A method of adjusting the rise time and fall time of output signals generated by a voltage-mode differential transmitter (VMT), the method comprising:

a) receiving at least one of a first output signal generated by a first driver of the VMT and a second output signal generated by a second driver of the VMT to obtain at least one received signal, the first driver including first inverter elements electrically connected to each other in parallel, the second driver including second inverter elements electrically connected to each other in parallel, each first inverter element and each second inverter element having a PMOS device and an NMOS device, the first output signal and the second output signal having a rise time and a fall time;

b) processing the at least one received signal to determine if there is difference between the fall time and the rise time; and

c) responsive to determining that there is a difference between the fall time and the rise time, modifying, in each of the first driver and the second driver, a ratio of a number of enabled PMOS devices to a number of enabled NMOS devices to reduce the difference between the fall time and the rise time.

2. The method of claim 1 wherein:

processing includes;

generating an indicator value indicative of one of the rise time being greater than the fall time and the rise time being smaller than the fall time; and

adding the indicator value to a counter;

and,

modifying the ratio of the number of enabled PMOS devices to the number of enabled NMOS devices is effected responsive to a counter value of the counter being outside a pre-determined counter value range.

3. The method of claim 2 wherein modifying the ratio of the number of enabled PMOS devices to the number of enabled NMOS devices is preceded by:

determining the counter value; and

responsive to the counter value being inside the pre-determined range, repeating actions a) and b).

4. The method of claim 1 wherein in each of the first driver and the second driver, the ratio of the number of enabled PMOS devices to the number of enabled NMOS devices is the same.

5. The method of claim 4 wherein the rise time is greater than the fall time and modifying, in each of the first driver and the second driver, the ratio of the number of enabled PMOS devices to the number of enabled NMOS devices includes decreasing the ratio.

6. The method of claim 4 wherein the rise time is smaller than the fall time and modifying, in each of the first driver and the second driver, the ratio of the number of enabled PMOS devices to the number of enabled NMOS devices includes increasing the ratio.

7. The method of claim 1 wherein receiving at least one of the first output signal and the second output signal consists in receiving only one of the first output signal and the second output signal.

8. The method of claim 1 wherein receiving at least one of the first output signal and the second output signal consists in receiving the first output signal and the second output signal.

9. The method of claim 1 wherein processing the at least one received signal includes comparing the at least one received signal to a reference signal.

10. The method of claim 9 wherein comparing the at least one received signal to a reference signal includes filtering the at least one received signal and the reference signal.

11. A method of adjusting the rise time and fall time of output signals generated by a composite voltage-mode differential transmitter (CVMT), the method comprising:

a) receiving at least one of a first output signal generated by a first set of drivers of the CVMT and a second output signal generated by a second set of drivers of the CVMT to obtain at least one received signal, the CVMT comprising unit cells, each unit cell having a driver of the first set of drivers and a driver of the second set of drivers, each driver of the first set of drivers including first inverter elements electrically connected to each other in parallel, each driver of the second set of drivers including second inverter elements electrically connected to each other in parallel, each first inverter element and each second inverter element having a PMOS device and an NMOS device, the first output signal and the second output signal having a rise time and a fall time;

b) processing the at least one received signal to determine if there is difference between the fall time and the rise time; and

c) responsive to determining that there is a difference between the fall time and the rise time, modifying, in each of the first driver and the second driver of at least one unit cell, a ratio of a number of enabled PMOS devices to a number of enabled NMOS devices to reduce the difference between the fall time and the rise time.

12. A method of controlling an edge rate of output signals generated by a composite voltage-mode differential transmitter (CVMT), the method comprising:

a) determining an initial edge rate of a first output signal and a second output signal, the first output signal generated by a first set of drivers of the CVMT and the second output signal generated by a second set of drivers of the CVMT, the CVMT comprising unit cells, each unit cell having a driver of the first set of drivers and a driver of the second set of drivers, each driver of the first set of drivers including first inverter elements electrically connected to each other in parallel, each driver of the second set of drivers including second inverter elements electrically connected to each other in parallel, each first inverter element and each second inverter element having a PMOS device and an NMOS device, the first output signal and the second output signal having a rise time and a fall time; and

b) in accordance with the initial edge rate and, in accordance with a target edge rate, modifying, in each of the first driver and the second driver of at least one unit cell, a ratio of a number of enabled PMOS devices to a number of enabled NMOS devices to modify the edge rate of the first output signal and the second output signal.

13. A voltage mode transmitter comprising:

a) first drivers and second drivers, the first drivers electrically connected to each other in parallel, the second drivers electrically connected to each other in parallel, each first driver including first inverter elements electrically connected to each other in parallel, each second driver including second inverter elements electrically connected to each other in parallel, each first inverter element and each second inverter element having a PMOS device and an NMOS device;

b) sensor circuitry arranged to receive at least one of a first output signal produced by the first drivers and a second output signal produced by the second drivers, the first output signal and the second output signal having a rise time and a fall time, the sensor circuitry to determine, as function of the at least one of the first output signal and the second output signal, a difference between the rise time and the fall time, the sensor circuitry to generate a sensor circuitry output signal indicative of the difference between the rise and fall time;

c) controller circuitry arranged to receive the sensor circuitry output signal and to generate a control signal as a function of the sensor circuitry output signal; and

d) actuator circuitry arranged to receive the control signal, the actuator circuitry operationally coupled to the first drivers and to the second drivers, the actuator circuitry configured to enable or disable PMOS devices and to enable or disable NMOS devices in each of the first drivers and in each of the second drivers, as a function of the control signal, to reduce the difference between the fall time and the rise time.

14. The voltage mode transmitter of claim 13 wherein the sensor circuitry includes:

filter circuitry to filter the at least one of the first output signal and the second output signal to obtain a filtered transmitter signal, the filter circuitry also to filter a reference signal to obtain a filtered reference signal; and

comparator circuitry to receive the filtered transmitter signal and the filtered reference signal, the comparator to generate the sensor circuitry output signal as a function of the filtered transmitter signal and of the filtered reference signal.

15. The voltage mode transmitter of claim 14 wherein the sensor circuitry includes transmission gate circuitry to receive the first output signal and the second output signal, the transmission gate circuitry to provide the first output signal, the second output signal, or both the first output signal and the second output signal to the filter circuitry.

16. A voltage mode transmitter comprising:

a) first drivers and second drivers, the first drivers electrically connected to each other in parallel, the second drivers electrically connected to each other in parallel, each first driver including first inverter elements electrically connected to each other in parallel, each second driver including second inverter elements electrically connected to each other in parallel, each first inverter element and each second inverter element having a PMOS device and an NMOS device, the first drivers to produce a first output signal, the second drivers to produce a second output signal, the first output signal and the second output signal each having an edge rate; and

b) actuator circuitry arranged to receive an edge rate control signal, the actuator circuitry operationally coupled to the first drivers and to the second drivers, the actuator circuitry configured to enable or disable PMOS devices and to enable or disable NMOS devices in each of the first drivers and in each of the second drivers, as a function of the edge rate control signal, to control the edge rate of the first output signal and of the second output signal.