Multi-cascode amplifier bias techniques

• US 8,779,859 B2
• Filed: 08/08/2012
• Issued: 07/15/2014
• Est. Priority Date: 08/08/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Su, Wenjun, Narathong, Chiewcharn, Yin, Guangming, Hadjichristos, Aristotele
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US13/570,062
• Publication Number:
  US 20140043102A1
• Time in Patent Office: 706 Days
• Field of Search: 330/296, 330/311, 330/51
• US Class Current: 330/311
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence

Abstract

Techniques for generating bias voltages for a multi-cascode amplifier. In an aspect, a multi-cascode bias network is provided, each transistor in the bias network being a replica of a corresponding transistor in the multi-cascode amplifier, enabling accurate biasing of the transistors in the multi-cascode amplifier. In another aspect, a voltage supply for the multi-cascode amplifier is provided separately from a voltage supply for the replica bias network, to advantageously decouple variations in the amplifier voltage supply from the bias network voltage supply. In yet another aspect, the bias voltages of transistors in the multi-cascode amplifier may be configured by adjusting the impedance of resistive voltage dividers coupled to the transistor gate biases. As the gain of the amplifier depends on the bias voltages of the cascode amplifiers, the gain of the amplifier may be adjusted in this manner without introducing a variable gain element directly in the amplifier signal path.

Claims

1. An apparatus comprising:

multi-cascode bias transistors comprising first and second cascode bias transistors and an input bias transistor, the input bias transistor comprising a drain coupled to the source of the first cascode bias transistor; and

first and second impedance networks coupled to a first supply voltage for generating bias voltages for the first and second cascode bias transistors, respectively, at least one of the first and second impedance networks comprising a configurable impedance for adjusting at least one bias voltage for the first and second cascode bias transistors;

wherein the input bias transistor is biased to a gate voltage determined by a reference current through a transistor that is a replica of the input bias transistor.

2. The apparatus of claim 1, at least one configurable impedance comprising:

a switchable resistance network configured to adjust the resistance coupling the gate of the respective cascode bias transistor to ground.

3. The apparatus of claim 1, at least one configurable impedance comprising:

a switchable resistance network configured to adjust the resistance coupling the gate of the respective cascode bias transistor to a supply voltage.

4. The apparatus of claim 1, the multi-cascode bias transistors further comprising a third cascode bias transistor, the gate of the third cascode bias transistor being coupled to a configurable impedance network.

5. The apparatus of claim 1, further comprising at least one power-down switch selectively decoupling at least one of the impedance networks from the first supply voltage.

6. The apparatus of claim 1, the second cascode bias transistor comprising a drain directly coupled to the first supply voltage.

7. An apparatus comprising:

multi-cascode bias transistors comprising first and second cascode bias transistors and an input bias transistor, the input bias transistor comprising a drain coupled to the source of the first cascode bias transistor; and

a multi-cascode amplifier comprising;

a first cascode transistor comprising a gate coupled to the bias voltage of the first cascode bias transistor; and

a second cascode transistor comprising a gate coupled to the bias voltage of the second cascode bias transistor; and

an input transistor coupled to the source of the first cascode transistor, the input transistor comprising a gate coupled to the gate voltage of the input bias transistor.

8. The apparatus of claim 7, the multi-cascode amplifier coupled to a first supply voltage, and a reference current through a transistor that is a replica of the input bias transistor coupled to a second supply voltage separate from the first supply voltage.

9. The apparatus of claim 8, the second supply voltage being lower than the first supply voltage.

10. The apparatus of claim 7, the apparatus configurable to reduce at least one bias voltage for the first and second cascode bias transistors to reduce a gain of the multi-cascode amplifier.

11. The apparatus of claim 7, each of the multi-cascode bias transistors being configured to have a fixed current ratio relative to a corresponding transistor of the multi-cascode amplifier.

12. The apparatus of claim 7, further comprising:

first and second impedance networks coupled to a first supply voltage for generating bias voltages for the first and second cascode bias transistors, respectively, at least one of the first and second impedance networks comprising a configurable impedance for adjusting at least one bias voltage for the first and second cascode bias transistors.

13. An apparatus comprising:

multi-cascode bias transistors comprising first and second cascode bias transistors and an input bias transistor, the input bias transistor comprising a drain coupled to the source of the first cascode bias transistor; and

means for adjusting the bias voltage of at least one of the multi-cascode bias transistors by configuring a configurable impedance;

means for selectively decoupling at least one configurable impedance network from a first supply voltage.

14. The apparatus of claim 13, the means for adjusting the bias voltage comprising a switchable resistance network, the network comprising a plurality of switches, each switch coupled in series with a corresponding resistor, the plurality of series-coupled switches and resistors in turn coupled to each other in parallel.

15. The apparatus of claim 14, further comprising:

means for biasing the input bias transistor.

16. The apparatus of claim 13, further comprising:

means for generating a bias voltage for a third cascode bias transistor by configuring the impedance of a configurable resistance network.

17. A method comprising:

generating bias voltages for first and second cascode bias transistors, the generating comprising configuring the impedance of at least one configurable impedance network coupled to a first supply voltage to vary the voltage tapped from an impedance divider network; and

coupling the generated bias voltages to first and second cascode transistors, the first and second cascode bias transistors having fixed current ratios relative to the first and second cascode transistors, the source of the first cascode bias transistor coupled to the drain of an input bias transistor, the source of the first cascode transistor coupled to the drain of an input transistor;

wherein the input bias transistor is biased to a gate voltage determined by a reference current through a transistor that is a replica of the input bias transistor.

18. The method of claim 17, further comprising:

coupling the first supply voltage to the first and second cascode transistors; and

coupling a second supply voltage separate from the first supply voltage to a reference current used to bias the input bias transistor.

19. The method of claim 17, further comprising:

adjusting the gain of a variable-gain amplifier by configuring the impedance of the at least one configurable impedance.