Power amplifier

• US 8,779,860 B2
• Filed: 08/15/2012
• Issued: 07/15/2014
• Est. Priority Date: 08/15/2012
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP (Singapore) PTE Limited (Broadcom, Inc.)
• Inventors: Jeon, Moon Suk, Jung, Sang Hwa, Kim, Jung Hyun, Kwon, Young, Woo, Jung Rin
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US13/586,218
• Publication Number:
  US 20140049322A1
• Time in Patent Office: 699 Days
• Field of Search: 330/277, 330/296, 330/302, 330/311
• US Class Current: 330/311
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal

Abstract

A power amplifier comprises a common source amplification stage and a first common gate amplification stage. The common source amplification stage includes a common source transistor for receiving a radio frequency (RF) input signal via a gate. The first common gate amplification stage is connected in cascode between a variable supply voltage source and the common source amplification stage, and amplifies an output of the common source amplification stage. The first common gate amplification stage includes a first common gate transistor, and a first gate bias controller configured to generate a first divided voltage based on a variable supply voltage of the variable supply voltage source, and to supply a first gate bias voltage generated by buffering the first divided voltage to a gate of the first common gate transistor.

Claims

1. A power amplifier, comprising:

a common source amplification stage including a common source transistor configured to receive a radio frequency (RF) input signal via a gate of the common source transistor; and

a first common gate amplification stage connected in cascode between a variable supply voltage source and the common source amplification stage, and configured to amplify an output of the common source amplification stage,

wherein the first common gate amplification stage includes;

a first common gate transistor connected in cascode to the common source transistor; and

a first gate bias controller configured to generate a first divided voltage based on a variable supply voltage of the variable supply voltage source, to generate a first gate bias voltage by buffering the first divided voltage, and to supply the first gate bias voltage to a gate of the first common gate transistor.

2. The power amplifier of claim 1, wherein the first gate bias controller shorts the first common gate transistor when the variable supply voltage is lower than a first reference voltage.

3. The power amplifier of claim 1, wherein the first gate bias controller includes:

a first voltage divider circuit connected to the variable supply voltage source, and configured to output the first divided voltage; and

a first unity-gain buffer including an input terminal connected to an output terminal of the first voltage divider circuit and an output terminal connected to the gate of the first common gate transistor, and configured to output the first gate bias voltage.

4. The power amplifier of claim 3, wherein the first gate bias controller further includes a first inductor connected between the first unity-gain buffer and the gate of the first common gate transistor.

5. The power amplifier of claim 3, wherein the first gate bias controller includes:

a first fixed supply voltage switch connected between the output terminal of the first unity-gain buffer and a fixed supply voltage source; and

a first comparator configured to compare the first reference voltage with the variable supply voltage, and to short the first common gate transistor by turning on the first fixed supply voltage switch when the variable supply voltage is lower than the first reference voltage.

6. The power amplifier of claim 5, wherein the first comparator cuts off a power supply to the first unity-gain buffer when the variable supply voltage is lower than the first reference voltage.

7. The power amplifier of claim 5, wherein the first comparator floats a first RF short capacitor connected between the gate of the first common gate transistor and a grounded node when the variable supply voltage is lower than the first reference voltage.

8. The power amplifier of claim 1, further comprising a second common gate amplification stage connected in cascode between the variable supply voltage source and the first common gate amplification stage,

wherein the second common gate amplification stage includes:

a second common gate transistor connected in cascode to the first common gate transistor; and

a second gate bias controller configured to generate a second divided voltage based on the variable supply voltage, to generate a second gate bias voltage by buffering the second divided voltage, and to supply the second gate bias voltage to a gate of the second common gate transistor.

9. The power amplifier of claim 8, wherein the second gate bias controller shorts the second common gate transistor when the variable supply voltage is lower than a second reference voltage.

10. The power amplifier of claim 9, wherein the first gate bias controller shorts the first common gate transistor if the variable supply voltage is lower than a first reference voltage, and the first reference voltage is lower than the second reference voltage.

11. The power amplifier of claim 5, wherein the second gate bias controller includes:

a second voltage divider circuit connected to the variable supply voltage source, and configured to output the second divided voltage; and

a second unity-gain buffer including an input terminal connected to an output terminal of the second voltage divider circuit and an output terminal connected to the gate of the second transistor, and configured to output the second gate bias voltage.

12. The power amplifier of claim 1, wherein the second gate bias controller further includes:

a second fixed supply voltage switch connected between the output terminal of the second unity-gain buffer and a fixed supply voltage source; and

a second comparator configured to compare the second reference voltage with the variable supply voltage, and to short the second common gate transistor by turning on the second fixed supply voltage switch when the variable supply voltage is lower than the second reference voltage.

13. The power amplifier of claim 12, wherein the second comparator cuts off a power supply to the second unity-gain buffer when the variable supply voltage is lower than the second reference voltage.

14. The power amplifier of claim 12, wherein the second comparator floats a second RF short capacitor connected between the gate of the second common gate transistor and a grounded node when the variable supply voltage is lower than the second reference voltage.

15. The power amplifier of claim 1, wherein the variable supply voltage is determined based on an envelope signal of the RF input signal.