Display panel and display apparatus having the same

• US 8,780,032 B2
• Filed: 10/14/2013
• Issued: 07/15/2014
• Est. Priority Date: 12/04/2006
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Lee, Min-Cheol, Park, Hee-Bum, Lee, Yong-Soon, Baek, Seung-Soo, Jeon, Sang-Jin
• Primary Examiner(s): Nguyen, Kevin M
• Application Number:
  US14/053,229
• Publication Number:
  US 20140043308A1
• Time in Patent Office: 274 Days
• Field of Search: 345/206, 345/98
• US Class Current: 345/98
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Claims

1. A display panel comprising:

an array substrate including gate lines and source lines, a gate driving part outputting gate signals to the gate line, and first and second clock lines connected to the gate driving part to respectively transmitting first and second clock signals to the gate driving part, the first and second clock lines connected to the gate driving part having substantially the same length; and

an opposite substrate combined with the array substrate and including a common electrode layer,

wherein a first time constant of the first clock signal and a second time constant of the second clock signal are substantially the same, and wherein the first clock signal and the second clock signal are transmitted to the same gate driving part.

2. The display panel of claim 1, wherein a first line resistance of the first clock line and a second line resistance of the second clock line are substantially the same.

3. The display panel of claim 2, wherein a first line capacitance of the first clock line and a second line capacitance of the second clock line are substantially the same.

4. The display panel of claim 3, wherein the common electrode layer has an opening portion patterned to expose the first and second clock lines, and exposed portions of the first and second clock lines have substantially the same area.

5. The display panel of claim 4, further comprising a sealant formed around the array substrate to combine the array substrate with the opposite substrate,

wherein areas of the first and second clock lines covered by the sealant are substantially the same.

6. The display panel of claim 3, further comprising a sealant formed around the array substrate to combine the array substrate with the opposite substrate,

wherein areas of the first and second clock lines covered by the sealant are substantially the same.

7. The display panel of claim 2, further comprising first and second pad electrodes respectively formed at end portions of the first and second clock lines on the array substrate,

wherein areas of the first and second pad electrodes are substantially the same.

8. The display panel of claim 1, wherein a first line capacitance of the first clock line and a second line capacitance of the second clock line are substantially the same.

9. The display panel of claim 8, wherein the common electrode layer has an opening portion patterned to expose the first and second clock lines, and exposed portions of the first and second clock lines have substantially the same area.

10. The display panel of claim 9, further comprising a sealant formed around the array substrate to combine the array substrate with the opposite substrate,

wherein areas of the first and second clock lines covered by the sealant are substantially the same.

11. The display panel of claim 8, further comprising a sealant formed around the array substrate to combine the array substrate with the opposite substrate,

wherein areas of the first and second clock lines covered by the sealant are substantially the same.

12. The display panel of claim 1, wherein the gate driving part comprises:

a first gate driving part formed in a first peripheral area adjacent to a first end portion of the gate lines to output the gate signals to the gate lines; and

a second gate driving part formed in a second peripheral area adjacent to a second end portion of the gate lines to output the gate signals to the gate lines.