Integrated circuit self aligned 3D memory array and manufacturing method
First Claim
1. A memory device, comprising:
- a substrate;
a stack of conductive strips, including a first one of the conductive strips with a first current path, and a second one of the conductive strips with a second current path;
a first gate structure and a second gate structure over the stack of conductive strips at different positions along the stack of conductive strips, the first gate structure and the second gate structure substantially perpendicular to the substrate, wherein the first gate structure is electrically coupled to multiple conductive strips in the stack of conductive strips;
a first memory element between the first current path and the first gate structure; and
a second memory element between the first current path and the second gate structure.
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Accused Products
Abstract
A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.
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Citations
20 Claims
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1. A memory device, comprising:
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a substrate; a stack of conductive strips, including a first one of the conductive strips with a first current path, and a second one of the conductive strips with a second current path; a first gate structure and a second gate structure over the stack of conductive strips at different positions along the stack of conductive strips, the first gate structure and the second gate structure substantially perpendicular to the substrate, wherein the first gate structure is electrically coupled to multiple conductive strips in the stack of conductive strips; a first memory element between the first current path and the first gate structure; and a second memory element between the first current path and the second gate structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory device, comprising:
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a substrate; a plurality of stacked bit lines over the substrate; a word line over the plurality of stacked bit lines, the word line including a conductive horizontal strip and a conductive vertical extension coupled to the conductive horizontal strip; a first memory cell disposed between one bit line of the plurality of stacked bit lines and the word line; and a second memory cell disposed between another bit line of the plurality of stacked bit lines and the word line, wherein the first memory cell and the second memory cell are at different levels from the substrate. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification