Semiconductor memory device and method of performing burn-in test on the same

• US 8,780,617 B2
• Filed: 10/17/2012
• Issued: 07/15/2014
• Est. Priority Date: 12/08/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Sang-beom, Lee, Joon-hyung
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US13/653,782
• Publication Number:
  US 20130148405A1
• Time in Patent Office: 636 Days
• Field of Search: 365/148, 365/163, 365/158, 365/171, 365/173, 365/201, 365/189.09, 365/189.11, 365/191, 365/230.06
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2029/1802 Address decoder
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device includes a cell array having a plurality of memory cells, each memory cell including a resistive element and a cell transistor between a bit line and a source line, and a source line voltage supply unit configured to supply, in a normal mode, a reference source line voltage to the source line, and in a test mode, a first source line voltage to the source line when data in a first state is recorded and a second source line voltage to the source line when data in a second state is recorded, the first source line voltage being lower than the reference source line voltage, and the second source line voltage being higher than the reference source line voltage.

Claims

1. A semiconductor memory device, comprising:

a cell array having a plurality of memory cells, each memory cell including a resistive element and a cell transistor between a bit line and a source line; and

a source line voltage supply unit configured to supply a reference source line voltage, a first source line voltage, and a second source line voltage,

wherein, in a normal mode, the source line voltage supply unit supplies the reference source line voltage to the source line,

wherein, in a test mode, the source line voltage supply unit supplies the first source line voltage to the source line when data in a first state is recorded and the second source line voltage to the source line when data in a second state is recorded, and

wherein the first source line voltage is lower than the reference source line voltage and the second source line voltage is higher than the reference source line voltage.

2. The semiconductor memory device as claimed in claim 1, wherein the memory cells include magnetic tunnel junction (MTJ) cells.

3. The semiconductor memory device as claimed in claim 2, wherein the test mode is a burn-in test mode.

4. The semiconductor memory device as claimed in claim 1, wherein the cell array includes a plurality of regions, the source line voltage supply unit being configured to supply source line voltages having different levels to the plurality of regions in the test mode.

5. The semiconductor memory device as claimed in claim 1, wherein, in the test mode, the source line voltage supply unit supplies source line voltages having a same level to the plurality of memory cells of the cell array.

6. The semiconductor memory device as claimed in claim 1, further comprising:

a row decoder configured to drive a word line connected to the memory cell in response to a first select signal;

a column decoder configured to select the bit line in response to a second select signal; and

a burn-in test decoder that, in the test mode, is configured to generate the first and second select signals for testing the memory cells.

7. The semiconductor memory device as claimed in claim 6, wherein all of the plurality of memory cells of the cell array are simultaneously selected in response to the first and second select signals.

8. The semiconductor memory device as claimed in claim 6, wherein the cell array includes a plurality of regions, memory cells of the plurality of regions are sequentially selected in response to the first and second select signals.

9. The semiconductor memory device as claimed in claim 1, wherein the source line voltage supply unit includes:

a first voltage generator configured to output the reference source line voltage;

a second voltage generator configured to output the first source line voltage or the second source line voltage according to a data write state; and

a switching unit configured to selectively supply any one of outputs of the first and second voltage generators to the source line in response to a test operation signal.

10. The semiconductor memory device as claimed in claim 1, wherein the source line voltage supply unit includes:

a voltage divider configured to generate a plurality of divided voltages through voltage division, and to output any one divided voltage in response to a test operation signal and at least one control signal; and

a voltage controller configured to receive the divided voltage, to output a source line voltage to the source line, and to adjust and output the source line voltage according to a level difference between the divided voltage and the source line voltage.

11. A method of performing a burn-in test on a semiconductor memory device having a cell array with a plurality of memory cells, each of the memory cells including a resistive element, the method comprising:

entering a burn-in test mode in response to a test operation signal;

selecting at least one memory cell of the cell array by using a burn-in test decoder;

supplying a first source line voltage lower than a reference source line voltage to a source line, such that data in a first state is written to the at least one selected memory cell; and

supplying a second source line voltage higher than the reference source line voltage to the source line, such that data in a second state is written to the at least one selected memory cell.

12. The method as claimed in claim 11, wherein, in a normal mode, the reference source line voltage is supplied to the source line in order to write data in the first state and the second state.

13. The method as claimed in claim 11, further comprising, when the semiconductor memory device operates in a normal mode, commonly supplying the reference source line voltage to the plurality of memory cells of the cell array through the source line.

14. The method as claimed in claim 11, wherein the memory cells include magnetic tunnel junction (MTJ) cells.

15. The method as claimed in claim 11, wherein, in a burn-in test mode, the plurality of memory cells of the cell array are simultaneously selected by using the burn-in test decoder.

16. The method as claimed in claim 11, wherein the cell array includes a plurality of regions, the plurality of regions of the cell array being sequentially selected in the burn-in test mode by using the burn-in test decoder.