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Semiconductor memory device and method of performing burn-in test on the same

  • US 8,780,617 B2
  • Filed: 10/17/2012
  • Issued: 07/15/2014
  • Est. Priority Date: 12/08/2011
  • Status: Active Grant
First Claim
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1. A semiconductor memory device, comprising:

  • a cell array having a plurality of memory cells, each memory cell including a resistive element and a cell transistor between a bit line and a source line; and

    a source line voltage supply unit configured to supply a reference source line voltage, a first source line voltage, and a second source line voltage,wherein, in a normal mode, the source line voltage supply unit supplies the reference source line voltage to the source line,wherein, in a test mode, the source line voltage supply unit supplies the first source line voltage to the source line when data in a first state is recorded and the second source line voltage to the source line when data in a second state is recorded, andwherein the first source line voltage is lower than the reference source line voltage and the second source line voltage is higher than the reference source line voltage.

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