Non-volatile memory devices having uniform error distributions among pages

• US 8,780,627 B1
• Filed: 01/13/2014
• Issued: 07/15/2014
• Est. Priority Date: 07/29/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Yang, Xueshi
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): RADKE, JAY W
• Application Number:
  US14/153,987
• Time in Patent Office: 183 Days
• Field of Search: 365/185.03, 365/185.18
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure containing a group of memory cells that are programmable based on a group of programming voltages, each of the memory cells being configured to represent two or more bits by a charge level, the two or more bits corresponding to two or more bit positions. The described system includes circuitry configured to monitor read-back data from the non-volatile memory structure, determine estimated mean and standard deviation values of level distributions of the memory cells based on the read-back data, and adjust one or more of the programming voltages based on the estimated mean and standard deviations of the level distribution such that differences among bit error rates of the bit positions are reduced.

Claims

1. An apparatus, comprising:

circuitry configured to monitor read-back data from a group of memory cells that are programmable based on a group of programming voltages, each of the memory cells being configured to represent two or more bits by a charge level, the two or more bits corresponding to two or more bit positions;

circuitry configured to determine estimated mean and standard deviation values of level distributions of the memory cells based on the read-back data; and

circuitry configured to adjust one or more of the programming voltages based on the estimated mean and standard deviations of the level distribution such that differences among bit error rates of the bit positions are reduced.

2. The apparatus of claim 1, wherein the bit positions include a first bit position and a second bit position, wherein the first bit position is associated with a first physical page, wherein the second bit position is associated with a second physical page.

3. The apparatus of claim 2, wherein the circuitry configured to adjust comprises circuitry configured to adjust the programming voltages to reduce differences among bit error rates of the physical pages.

4. The apparatus of claim 1, wherein the circuitry configured to adjust comprises circuitry configured to select the programming voltages such that two or more crossing-over probabilities of neighboring states of the two or more bits are different.

5. The apparatus of claim 1, comprising:

circuitry configured to determine detection threshold values based on the estimated mean and standard deviation values; and

circuitry configured to use the detection threshold values for interpreting values associated with read-back data from the memory cells.

6. The apparatus of claim 1, wherein the one or more of the programming voltages are adjusted in response to a change in bit error rates of individual bit positions.

7. The apparatus of claim 1, wherein the one or more of the programming voltages are adjusted in response to a predetermined number of writes, reads, or both.

8. The apparatus of claim 1, comprising:

a memory configured to store the programming voltages, and any adjustments thereto.

9. The apparatus of claim 1, wherein the memory cells include flash memory cells.

10. A system comprising:

a non-volatile memory structure comprising a group of memory cells that are programmable based on a group of programming voltages, each of the memory cells being configured to represent two or more bits by a charge level, the two or more bits corresponding to two or more bit positions; and

circuitry configured to monitor read-back data from the non-volatile memory structure, determine estimated mean and standard deviation values of level distributions of the memory cells based on the read-back data, and adjust one or more of the programming voltages based on the estimated mean and standard deviations of the level distribution such that differences among bit error rates of the bit positions are reduced.

11. The system of claim 10, wherein the bit positions include a first bit position and a second bit position, wherein the first bit position is associated with a first physical page, wherein the second bit position is associated with a second physical page.

12. The system of claim 11, wherein the circuitry configured to adjust comprises circuitry configured to adjust the programming voltages to reduce differences among bit error rates of the physical pages.

13. The system of claim 10, wherein the circuitry configured to adjust comprises circuitry configured to adjust the programming voltages such that two or more crossing-over probabilities of neighboring states of the two or more bits are different.

14. The system of claim 10, wherein the circuitry comprises:

circuitry configured to determine detection threshold values based on the estimated mean and standard deviation values; and

circuitry configured to use the detection threshold values for interpreting values associated with read-back data from the memory cells.

15. The system of claim 10, wherein the one or more of the programming voltages are adjusted in response to a change in bit error rates of individual bit positions.

16. The system of claim 10, wherein the one or more of the programming voltages are adjusted in response to a predetermined number of writes, reads, or both.

17. The system of claim 10, comprising:

a memory configured to store the programming voltages, and any adjustments thereto.

18. The system of claim 10, wherein the memory cells include flash memory cells.

19. A method comprising:

determining one or more voltage level distributions associated with a group of memory cells, each of the memory cells being configured to represent two or more bits by a charge level, the two or more bits corresponding to two or more bit positions, the group of memory cells being programmed based on a group of programming voltages; and

adjusting one or more of the programming voltages based on the one or more voltage level distributions such that differences among bit error rates of the bit positions are reduced.

20. The method of claim 19, wherein the bit positions include a first bit position and a second bit position, wherein the first bit position is associated with a first physical page, wherein the second bit position is associated with a second physical page.

21. The method of claim 20, wherein adjusting the one or more of the programming voltages comprises adjusting the one or more of the programming voltages to reduce differences among bit error rates of the physical pages.

22. The method of claim 19, wherein adjusting the one or more of the programming voltages comprises adjusting the one or more of the programming voltages such that at least two or more crossing-over probabilities of neighboring states, which are associated with two or more bits of a memory cell, are different.

23. The method of claim 19, comprising:

determining when to adjust the one or more of the programming voltages based on a change in bit error rates of individual bit positions.

24. The method of claim 19, comprising:

determining when to adjust the one or more of the programming voltages based on a predetermined number of writes, reads, or both.

25. The method of claim 19, comprising:

storing the programming voltages, and any adjustments thereto, in a memory.

26. The method of claim 19, wherein the memory cells include flash memory cells.