Memory devices having data lines included in top and bottom conductive lines

• US 8,780,631 B2
• Filed: 08/21/2012
• Issued: 07/15/2014
• Est. Priority Date: 08/21/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US13/590,964
• Publication Number:
  US 20140056049A1
• Time in Patent Office: 693 Days
• Field of Search: 365/185.17, 365/185.21
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a first set of data lines. At least a portion of the second set of conductive lines is configured as a second set of data lines. Each of the memory strings is coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines. Other embodiments including additional apparatuses and methods are described.

Claims

1. An apparatus comprising:

a first set of conductive lines located on a first level of the apparatus, at least a portion of the first set of conductive lines configured as a first set of data lines;

a second set of conductive lines located on a second level of the apparatus, at least a portion of the second set of conductive lines configured as a second set of data lines; and

memory cells located in different levels of the apparatus and arranged in memory cell strings, each of the memory strings coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines.

2. The apparatus of claim 1, wherein the first set of conductive lines includes a first conductive line, a second conductive line, a third conductive line, and a fourth conductive line, the second conductive line arranged between the first and third conductive lines, the third conductive line arranged between the second and fourth conductive lines, wherein the first and third conductive lines are included in the first set of data lines, and the second and fourth conductive line are excluded from the first set of data lines.

3. The apparatus of claim 2, wherein the second set of conductive lines includes a fifth conductive line, a sixth conductive line, a seventh conductive line, and an eighth conductive line, the sixth conductive line arranged between the fifth and seven conductive lines, the seven conductive line arranged between the sixth and eighth conductive lines, wherein the sixth and eighth conductive lines are included in the second set of data lines, and the fifth and seven conductive lines are excluded from the second set of data lines.

4. The apparatus of claim 3, wherein the memory cell string includes a first memory cell string coupled to the first and fifth conductive lines, and a second memory cell string coupled to the second and sixth conductive lines.

5. The apparatus of claim 1, further comprising sense circuits, each of the sense circuits coupled to a respective data line in the first and second set of data lines, wherein a quantity of the sense circuits is equal to a quantity of the data lines in the first and second set of data lines.

6. The apparatus of claim 1, further including a substrate, wherein one of the first and second sets of data lines is located between the substrate and the memory cells.

7. The apparatus of claim 1, wherein the apparatus comprises a memory device.

8. The apparatus of claim 1, wherein the apparatus comprises a system including a memory device that includes the conductive lines and the memory cells.

9. A method comprising:

applying a signal to memory cells arranged in a row in a device

obtaining information from a first portion of the memory cells through a first set of data lines located in a first level of the device; and

obtaining information from a second portion of the memory cells through a second set of data lines located in a second level of the device.

10. The method of claim 9, further comprising:

coupling a data line in the first set of data line to a node; and

coupling the node to a supply node; and

decoupling the data line from the node.

11. The method of claim 10, further comprising:

decoupling the data line from the supply node; and

coupling the data line to the node.

12. The method of claim 11, further comprising:

generating a signal to indicate a state of a memory cell coupled to the data line.