Power amplification based on phase angle controlled reference signal and amplitude control signal

• US 8,781,418 B2
• Filed: 03/21/2012
• Issued: 07/15/2014
• Est. Priority Date: 10/22/2004
• Status: Active Grant

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Sorrells, David F., Rawlins, Gregory S., Rawlins, Michael W.
• Primary Examiner(s): Le, Lana N
• Application Number:
  US13/425,947
• Publication Number:
  US 20120243637A1
• Time in Patent Office: 846 Days
• Field of Search: 455/102, 455108-113, 4551271-1275, 455/126, 455/114.3, 330/10, 330295-297, 330/93
• US Class Current: 455/127.1
• CPC Class Codes: H03C 5/00 Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal H03C7/00 takes precedence
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0233 by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
• CPC Class Codes: H03F 1/0294 using vector summing of two or more constant amplitude phase-modulated signals
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 1/3205 in field-effect transistor amplifiers
• CPC Class Codes: H03F 1/3223 using feed-forward H03F1/3211 takes precedence
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2201/3215 To increase the output power or efficiency
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45071 with semiconductor devices only
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/0483 : Transmitters with multiple parallel paths
• CPC Class Codes: H04B 2001/045 : with means for improving efficiency
• CPC Class Codes: H04B 2001/0491 : with frequency synthesizers, frequency converters or modulators
• CPC Class Codes: H04L 27/20 : Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/36 : Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/362 : Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence

Abstract

Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Claims

1. An apparatus for power amplification, comprising;

input circuitry configured to receive information and to generate in-phase and quadrature phase amplitude control signals and in-phase and quadrature phase control signals from said received information;

first vector modulation circuitry, coupled to said input circuitry, configured to receive a frequency reference signal and said in-phase and quadrature phase control signals and to generate a phase angle controlled frequency reference signal;

second vector modulation circuitry, coupled to said input circuitry and said first vector modulation circuitry, configured to receive said in-phase and quadrature phase amplitude control signals and said phase angle controlled frequency reference signal first and second substantially constant envelope signals using said phase angle controlled frequency reference signal and said in-phase and quadrature phase amplitude control signals; and

power amplification circuitry, coupled to said second vector modulation circuitry, that comprises two or more circuit branches each comprising one or more transistors, wherein outputs of said one or more transistors in said two or more circuit branches form a single circuit node, and wherein said first and second substantially constant envelope signals are simultaneously amplified and combined at said single circuit node of said power amplification circuitry to create a desired output signal.

2. The apparatus of claim 1, wherein said received information comprises one or more baseband information signals.

3. The apparatus of claim 2, further comprising:

biasing control circuitry coupled to said power amplification circuitry.

4. The apparatus of claim 1, wherein said received information comprises in-phase and quadrature phase baseband information signals.

5. The apparatus of claim 1, wherein said received information comprises analog in-phase and analog quadrature phase baseband information signals.

6. The apparatus of claim 1, wherein said received information comprises digital in-phase and digital quadrature phase baseband information signals.

7. The apparatus of claim 1, wherein said received information comprises a time-varying radio frequency (RF) signal.

8. The apparatus of claim 1, wherein said received information comprises in-phase and quadrature phase radio frequency (RF) signals.

9. The apparatus of claim 1, further comprising:

one or more digital-to-analog converters coupled between said input circuitry and said first and second vector modulation circuitry.

10. The apparatus of claim 9, further comprising:

one or more anti-aliasing filters coupled to outputs of said one or more digital-to-analog converters.

11. The apparatus of claim 9, further comprising:

one or more interpolation filters coupled to outputs of said one or more digital-to-analog converters.

12. The apparatus of claim 1, further comprising:

a synthesizer configured to generate said frequency reference signal.

13. The apparatus of claim 1, wherein said input circuitry comprises one or more digital-to-analog converters configured to convert from digital to analog said in-phase and quadrature phase amplitude control signals and said in-phase and quadrature phase control signals.

14. The apparatus of claim 1, wherein said input circuitry is configured to generate analog in-phase and quadrature phase amplitude control signals and said in-phase and quadrature phase control signals.

15. The apparatus of claim 1, wherein said input circuitry is configured to generate said in-phase and quadrature phase amplitude control signals from said received information and transfer functions, said transfer functions enabling said power amplification circuitry to simultaneously amplify and combine said substantially constant envelope signals at said single circuit node.

16. The apparatus of claim 1, wherein said input circuitry comprises digital circuitry configured to process said received information and to generate said in-phase and quadrature phase amplitude control signals and said in-phase and quadrature phase control signals.

17. The apparatus of claim 1, wherein said input circuitry comprises one or more lookup tables used to process said received information and to generate said in-phase and quadrature phase amplitude control signals.

18. The apparatus of claim 17, further comprising:

interpolation circuitry configured to interpolate between values in said one or more look up tables.

19. The apparatus of claim 1, wherein said input circuitry comprises:

means for determining magnitude information from said received information; and

means for processing said determined magnitude information to generate said in-phase and quadrature phase amplitude control signals.

20. The apparatus of claim 1, wherein said input circuitry comprises transfer function circuitry configured to determine magnitude information from said received information.

21. The apparatus of claim 20, wherein said transfer function circuitry comprises means for determining a complex envelope from said received information.

22. The apparatus of claim 21, wherein said transfer function circuitry further comprises:

means for determining a phase shift angle using said complex envelope, wherein said phase shift angle is equal to a phase difference between said first and second substantially constant envelope signals; and

means for processing said phase shift angle to generate said in-phase and quadrature phase amplitude control signals.

23. The apparatus of claim 22, wherein said means for determining a phase shift angle implements the function:

24. The apparatus of claim 22, wherein said means for processing generates said in-phase and quadrature phase amplitude control signals according to:

25. The apparatus of claim 22, wherein said means for determining a phase shift angle implements a function mathematically equivalent to:

26. The apparatus of claim 22, wherein said means for processing generates said in-phase and quadrature phase amplitude control signals according to functions mathematically equivalent to:

27. The apparatus of claim 1, wherein said input circuitry comprises:

means for generating in-phase and quadrature phase control signals from the received information.

28. The apparatus of claim 1, wherein said first vector modulation circuitry comprises:

means for generating a plurality of secondary frequency reference signals from said frequency reference signal, wherein one or more of said plurality of secondary frequency reference signals are phase shifted relative to said frequency reference signal;

means for multiplying said plurality of secondary frequency reference signals by respective said in-phase and quadrature phase control signals to generate controlled secondary frequency reference signals; and

means for combining subsets of said controlled secondary frequency reference signals to generate said phase angle controlled frequency reference signal.

29. The apparatus of claim 28, wherein said means for generating said plurality of secondary frequency reference signals comprises means for generating in-phase and quadrature phase secondary frequency reference signals relative to said frequency reference signal.

30. The apparatus of claim 29, wherein said means for multiplying comprises means for multiplying the in-phase secondary frequency reference signals by the in-phase amplitude control signals and the quadrature phase secondary frequency reference signals by the quadrature phase amplitude control signals.

31. The apparatus of claim 28, wherein said means for generating said plurality of secondary frequency reference signals comprises one or more phase splitters.

32. The apparatus of claim 28, wherein said means for multiplying comprises one or more vector modulators.

33. The apparatus of claim 28, wherein said means for multiplying comprises one or more mixers.

34. The apparatus of claim 28, wherein said means for combining comprises one or more summing circuits.

35. The apparatus of claim 1, wherein said second vector modulation circuitry comprises:

means for generating a plurality of ternary frequency reference signals from said phase angle controlled frequency reference signal, wherein one or more of said plurality of ternary frequency reference signals are phase shifted relative to said phase angle controlled frequency signal;

means for multiplying said plurality of ternary frequency reference signals by respective said in-phase and quadrature phase amplitude control signals to generate controlled ternary frequency reference signals; and

means for combining subsets of said controlled ternary frequency reference signals to generate said first and second substantially constant envelope signals.

36. The apparatus of claim 35, wherein said means for generating said plurality of ternary frequency reference signals comprises means for generating in-phase and quadrature phase ternary frequency reference signals relative to said phase angle controlled frequency signal.

37. The apparatus of claim 36, wherein said means for multiplying comprises means for multiplying the in-phase ternary frequency reference signals by the in-phase amplitude control signals and the quadrature phase ternary frequency reference signals by the quadrature phase amplitude control signals.

38. The apparatus of claim 35, wherein said means for generating said plurality of ternary frequency reference signals comprises one or more phase splitters.

39. The apparatus of claim 35, wherein said means for multiplying comprises one or more vector modulators.

40. The apparatus of claim 35, wherein said means for multiplying comprises one or more mixers.

41. The apparatus of claim 35, wherein said means for combining comprises one or more summing circuits.

42. The apparatus of claim 1, wherein said power amplification circuitry comprises one or more harmonic control circuits.

43. The apparatus of claim 1, wherein said power amplification circuitry comprises one or more power amplification sub-stages.

44. The apparatus of claim 1, wherein said power amplification circuitry comprises bias control circuitry configured to control one or more of output power efficiency, output linearity, and amplification stage protection.

45. The apparatus of claim 1, wherein said power amplification circuitry comprises a multiple-input, single output (MISO) power amplifier.

46. The apparatus of claim 1, wherein said power amplification circuitry comprises a bias controlled multiple-input, single output (MISO) power amplifier.

47. The apparatus of claim 46, further comprising:

means for using a bias control function to control one or more of output power efficiency, output linearity, and amplification stage protection of said bias controlled MISO power amplifier.

48. The apparatus of claim 1, further comprising:

means for dynamically controlling said one or more transistors in said two or more circuit branches to transition operation of said one or more transistors along an operational range that includes a switching amplifier operation and a current source amplifier operation.

49. The apparatus of claim 1, further comprising:

means for simultaneously controlling an input differential phase and a bias of said one or more transistors based on requirements of said desired output signal.

50. The apparatus of claim 1, wherein said power amplification circuitry comprises one or more non-linear amplifiers.

51. The apparatus of claim 1, wherein said power amplification circuitry comprises two or more collector- or emitter-coupled transistors.

52. The apparatus of claim 1, wherein said power amplification circuitry comprises two or more source- or drain-coupled transistors.

53. The apparatus of claim 1, wherein said power amplification circuitry comprises a plurality of npn and/or pnp transistors.

54. The apparatus of claim 1, wherein said power amplification circuitry comprises a plurality of NMOS and/or PMOS transistors.

55. The apparatus of claim 1, wherein said outputs of said one or more transistors in said two or more circuit branches are directly coupled together with substantially no or no resistive, inductive, or capacitive components.

56. The apparatus of claim 1, wherein said outputs of said one or more transistors in said two or more circuit branches are directly coupled together with substantially no electrical isolation and/or substantially no magnetic isolation.

57. The apparatus of claim 1, wherein said outputs of said one or more transistors in said two or more circuit branches are coupled together with a conductive wire.

58. The apparatus of claim 1, wherein said outputs of said one or more transistors in said two or more circuit branches are coupled together solely with a conductive wire.

59. The apparatus of claim 1, wherein said input circuitry comprises:

means for generating said control signals from said received information and transfer functions, said transfer functions enable enabling said simultaneous amplification and combination of said first and second substantially constant envelope signals at said single circuit node.

60. The apparatus of claim 59, wherein said transfer functions compensate for resistive, inductive, and capacitive elements between said outputs of said one or more transistors in said two or more circuit branches of said power amplification circuitry.

61. The apparatus of claim 59, wherein said transfer functions compensate for parasitic resistive, inductive, and capacitive elements between said outputs of said one or more transistors in said two or more circuit branches of said power amplification circuitry.

62. The apparatus of claim 59, wherein said transfer functions compensate for resistive, inductive, and capacitive components between said outputs of said one or more transistors in said two or more circuit branches of a multiple-input, single output (MISO) power amplifier.

63. The apparatus of claim 1, further comprising:

means for dynamically controlling said one or more transistors in said two or more circuit branches to transition operation of said one or more transistors along an operational range that includes a switching amplifier operation and a current source amplifier operation.

64. The apparatus of claim 1, wherein said outputs of said one or more transistors in said two or more circuit branches of said power amplification circuitry are coupled together at said single circuit node with parasitic resistive, inductive, or capacitive elements.

65. The apparatus of claim 1, wherein said outputs of said one or more transistors in said two or more circuit branches of said power amplification circuitry are coupled together at said single circuit node with substantially no electrical isolation.

66. The apparatus of claim 1, wherein output voltages of said one or more transistors in said two or more circuit branches of said power amplification circuitry are substantially equal to an output voltage of said power amplification circuitry for all operational instances of time of said power amplification circuitry.