Digital fast CORDIC for envelope tracking generation

• US 8,782,107 B2
• Filed: 11/16/2011
• Issued: 07/15/2014
• Est. Priority Date: 11/16/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Myara, David, Khlat, Nadim, Rafin, Jrmie
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US13/297,490
• Publication Number:
  US 20120121039A1
• Time in Patent Office: 972 Days
• Field of Search: 708/201, 708/441, 708/442
• US Class Current: 708/201
• CPC Class Codes: G06F 1/0307 Logarithmic or exponential functions G06F1/0314, G06F1/035 take precedence
• CPC Class Codes: G06F 7/556 Logarithmic or exponential functions
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03M 7/04 the radix thereof being two

Abstract

Disclosed is a coordinate rotation digital computer (CORDIC) having a maximum value circuit that selects a larger of the first component or the second component. A minimum value circuit selects a minimum operand that is a smaller one of the first component or the second component. Also included are N rotator stages, each corresponding to a unique one of N predetermined vectors, each of the N rotator stages having a first multiply circuit to multiply the maximum operand by a cosine coefficient of a predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the predetermined vector to output a second rotation component, and an adder circuit for adding the first rotation component to the second rotation component to output one of N results, and a maximum value circuit for outputting a maximum one of the N results.

Claims

1. A coordinate rotation digital computer (CORDIC) for computing a norm of a vector having a first component and a second component, comprising:

a first maximum value circuit for outputting a maximum operand that is a larger one of either an absolute value of the first component or an absolute value of the second component;

a minimum value circuit for outputting a minimum operand that is a smaller one of either an absolute value of the first component or an absolute value of the second component;

N rotator stages, each corresponding to a unique one of N predetermined vectors, each having a first multiply circuit for multiplying the maximum operand by a cosine coefficient of a corresponding predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the corresponding predetermined vector to output a second rotation component and an adder circuit for adding the first rotation component to the second rotation component to output one of N results; and

a second maximum value circuit for outputting a maximum one of the N results.

2. The CORD IC of claim 1 wherein the N predetermined vectors are unit vectors.

3. The CORD IC of claim 1 wherein each adder circuit of the N rotator stages comprises:

a results register having an overflow bit that is set when a result of an addition performed by the adder circuit is larger than the results register; and

a results multiplexer that outputs the result of an addition performed by the adder circuit if the overflow bit is not set or outputs a predetermined maximum value if the overflow bit is set.

4. The CORDIC of claim 1 wherein each adder circuit of the N rotator stages include a round and right shift (RS) circuit adapted to round addition results and then right shift the addition results until a predetermined bit wide result remains for output.

5. The CORDIC of claim 1 wherein each cosine coefficient a(i) is given by the following equation,

6. The CORDIC of claim 5 wherein each sine coefficient b(i) is given by the following equation,

7. The CORDIC of claim 6 wherein the dimensionless correction factor is given by the following equation,

8. The CORDIC of claim 1 further including mode circuitry adapted to output norms divided by the square root of two.

9. The CORDIC of claim 8 wherein the mode circuitry comprises:

an input adder circuit to add the first component to the second component;

a first divider circuit to divides results of the input adder circuit by two; and

a first multiplexer for selecting either the first component or the results of the input adder circuit divided by two.

10. The CORD IC of claim 9 wherein the mode circuitry further comprises:

an input subtractor circuit to subtract the second component from the first component;

a second divider circuit to divides results of the input adder circuit by two; and

a second multiplexer for selecting either the second component or the results of the input subtractor circuit divided by two.

11. An envelope tracking system comprising:

a power amplifier module (PAM);

a fast switch mode power supply (SMPS) converter adapted to supply modulated power to the PAM in response to an envelope tracking signal (ETS);

an envelope tracking signal (ETS) generator adapted to drive the SMPS converter in response to a stream of vector norms; and

a CORDIC for computing a stream of vector norms, each having a first component and a second component, comprising;

a first maximum value circuit for outputting a maximum operand that is a larger one of either an absolute value of the first component or an absolute value of the second component;

a minimum value circuit for outputting a minimum operand that is a smaller one of either an absolute value of the first component or an absolute value of the second component;

N rotator stages, each corresponding to a unique one of N predetermined vectors, each having a first multiply circuit for multiplying the maximum operand by a cosine coefficient of a corresponding predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the corresponding predetermined vector to output a second rotation component and an adder circuit for adding the first rotation component to the second rotation component to output one of N results; and

a second maximum value circuit for outputting a maximum one of the N results.

12. The envelope tracking system of claim 11 wherein the N predetermined vectors are unit vectors.

13. The envelope tracking system of claim 11 wherein each adder circuit of the N rotator stages comprises:

a results register having an overflow bit that is set when a result of an addition performed by the adder circuit is larger than the results register; and

a results multiplexer that outputs the result of an addition performed by the adder circuit if the overflow bit is not set or outputs a predetermined maximum value if the overflow bit is set.

14. The envelope tracking system of claim 11 wherein each adder circuit of the N rotator stages include a round and right shift (RS) circuit adapted to round addition results and then right shift the addition results until a predetermined bit wide result remains for output.

15. The envelope tracking system of claim 11 wherein each cosine coefficient a(i) is given by the following equation,

16. The envelope tracking system of claim 15 wherein each sine coefficient b(i) is given by the following equation,

17. The envelope tracking system of claim 16 wherein the dimensionless correction factor is given by the following equation,

18. The envelope tracking system of claim 11 further including mode circuitry adapted to output norms divided by the square root of two.

19. The envelope tracking system of claim 18 wherein the mode circuitry comprises:

an input adder circuit to add the first component to the second component;

a first divider circuit to divides results of the input adder circuit by two; and

a first multiplexer for selecting either the first component or the results of the input adder circuit divided by two.

20. The envelope tracking system of claim 19 wherein the mode circuitry further comprises:

an input subtractor circuit to subtract the second component from the first component; and

a second divider circuit to divides results of the input adder circuit by two; and

a second multiplexer for selecting either the second component or the results of the input subtractor circuit divided by two.