Scalable and configurable system on a chip interrupt controller

• US 8,782,314 B2
• Filed: 09/29/2011
• Issued: 07/15/2014
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kothari, Love, Fullerton, Mark
• Primary Examiner(s): Myers, Paul R
• Assistant Examiner(s): DALEY, CHRISTOPHER ANTHONY
• Application Number:
  US13/249,057
• Publication Number:
  US 20130046915A1
• Time in Patent Office: 1,020 Days
• Field of Search: 710/260, 710/317, 713/300
• US Class Current: 710/260
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

Embodiments include a system and method for an interrupt controller that propagates interrupts to a subsystem in a system-on-a-chip (SOC). Interrupts are provided to an interrupt controller that controls access of interrupts to a particular subsystem in the SOC that includes multiple subsystems. Each subsystem in the SOC generates multiple interrupts to other subsystems in the SOC. The interrupt controller processes multiple interrupts and generates an interrupt output. The interrupt output is then transmitted to a particular subsystem.

Claims

1. A method for propagating a plurality of interrupts to a subsystem in a system-on-a-chip (SOC), comprising:

providing the plurality of interrupts to an interrupt controller, the interrupt controller controlling access of the plurality of interrupts to the subsystem on the SOC, the SOC including a plurality of subsystems that generate the plurality of interrupts;

processing the plurality of interrupts using the interrupt controller to generate an interrupt output, wherein the processing further comprises;

partitioning the plurality of interrupts for processing by a plurality of subsections within the interrupt controller;

applying an interrupt mask to each interrupt within each subsection in the plurality of subsections, wherein the applying generates a masked interrupt from each interrupt; and

aggregating each masked interrupt in each subsection with other masked interrupts in the same subsection into the interrupt output; and

transmitting the interrupt output to the subsystem.

2. The method of claim 1, wherein the interrupt mask identifies logic within each subsection that processes the interrupt.

3. The method of claim 1, further comprising:

determining whether the subsystem is dormant; and

when the subsystem is dormant, waking up the subsystem prior to transmitting the interrupt output to the subsystem.

4. The method of claim 1, further comprising:

identifying a dedicated interrupt in the plurality of interrupts; and

routing the dedicated interrupt to the interrupt output, wherein the routing bypasses the processing using the interrupt controller.

5. The method of claim 1, further comprising:

generating an interrupt within the interrupt controller.

6. The method of claim 5, further comprising:

using the generated interrupt to test the processing in the interrupt controller.

7. A system for propagating a plurality of interrupts to a subsystem included on a system on a chip (SOC), comprising:

an interrupt controller including a plurality of subsections, the interrupt controller configured to;

receive the plurality of interrupts, the interrupt controller controlling access of the plurality of interrupts to the subsystem on the SOC, the SOC including a plurality of subsystems that generate the plurality of interrupts;

process the plurality of interrupts using the plurality of subsections to generate an interrupt output, wherein each subsection is configured to;

receive a subset of the plurality of interrupts;

apply an interrupt mask to each interrupt within the subset of interrupts to generate a masked interrupt for each interrupt; and

aggregate each masked interrupt within the subsection with other masked interrupts into the interrupt output; and

transmit the interrupt output to the subsystem.

8. The system of claim 7, wherein the interrupt mask identifies logic within each subsection that processes the interrupt.

9. The system of claim 7, further comprising a power source configured to:

determine whether the subsystem is dormant; and

when the subsystem is dormant, generate a signal to the subsystem, wherein the signal wakes up the subsystem prior to the interrupt controller transmitting the interrupt output to the subsystem.

10. The system of claim 7, wherein the interrupt controller is further configured to:

identify a dedicated interrupt in the plurality of interrupts; and

route the dedicated interrupt to the interrupt output, wherein the routing bypasses each subsection in the interrupt controller.

11. A method for propagating a plurality of interrupts within a subsystem included on a system on a chip (SOC), comprising:

providing the plurality of interrupts to an interrupt controller, the interrupt controller controlling access of the plurality of interrupts within the subsystem;

partitioning the plurality of interrupts for processing by a plurality of subsections within the interrupt controller;

applying an interrupt mask to each interrupt within each subsection in the plurality of subsections, wherein the applying generates a masked interrupt for each interrupt;

aggregating each masked interrupt in each subsection with the other masked interrupts in the same subsection into an interrupt output; and

using a cross-bar configuration to transmit the interrupt output of each subsection within the SOC.

12. The method of claim 11, wherein at least one interrupt in the plurality of interrupts is an internal interrupt.

13. The method of claim 11, wherein at least one interrupt in the plurality of interrupts is an external interrupt.

14. The method of claim 11, further comprising transmitting the interrupt output to another subsystem in the SOC.

15. The method of claim 11, further comprising transmitting the interrupt output to a mini-subsystem within the subsystem.

16. A system for propagating a plurality of interrupts within a subsystem in a system on a chip (SOC), comprising:

an interrupt controller configured to;

receive the plurality of interrupts within the subsystem;

partition the plurality of interrupts into a plurality of subsets for processing by a plurality of subsections within the interrupt controller, wherein each subsection within the plurality of subsections is configured to;

apply an interrupt mask to each interrupt within the interrupt subset to generate a masked interrupt for each interrupt; and

aggregate each masked interrupt in each subsection with the other masked interrupts in the same subsection into an interrupt output; and

use a cross-bar configuration to transmit the interrupt output of each subsection within the SOC.

17. The system of claim 16, wherein at least one interrupt in the plurality of interrupts is an internal interrupt.

18. The system of claim 16, wherein at least one interrupt in the plurality of interrupts is an external interrupt.

19. The system of claim 16, further comprising transmitting the interrupt output to another subsystem in the SOC.

20. The system of claim 16, further comprising transmitting the interrupt output to a mini-subsystem within the subsystem.