Power state synchronization in a multi-core processor
First Claim
1. A multi-core processor comprising:
- a plurality of physical processing cores; and
inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores;
wherein;
the inter-core state discover microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process; and
wherein each native instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the native instance;
each core has a target operating state;
the processor includes a domain comprising at least two of the microprocessor'"'"'s cores;
the processor provides a resource to the domain, which resource is shared by the cores of the domain;
the synchronization logic is configured to discover whether the domain is prepared to implement a restricted power-conserving operating state for the resource which would limit the power, speed, or efficiency with which the cores sharing the resource are able to operate; and
wherein the domain is prepared to implement the restricted operating state if any only if each of the enabled cores in the domain sharing the resource has a target operating state at least as restrictive as the restricted operating state.
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Abstract
A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications.
34 Citations
23 Claims
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1. A multi-core processor comprising:
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a plurality of physical processing cores; and inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores; wherein; the inter-core state discover microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process; and wherein each native instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the native instance; each core has a target operating state; the processor includes a domain comprising at least two of the microprocessor'"'"'s cores; the processor provides a resource to the domain, which resource is shared by the cores of the domain; the synchronization logic is configured to discover whether the domain is prepared to implement a restricted power-conserving operating state for the resource which would limit the power, speed, or efficiency with which the cores sharing the resource are able to operate; and wherein the domain is prepared to implement the restricted operating state if any only if each of the enabled cores in the domain sharing the resource has a target operating state at least as restrictive as the restricted operating state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A multi-core processor comprising:
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a plurality of physical processing cores; and inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores; wherein; the inter-core state discover microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process; and wherein each native instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the native instance; each core has a target operating state; the processor includes a domain comprising at least two of the microprocessor'"'"'s cores; the processor provides a resource to the domain, which resource is shared by the cores of the domain; and the synchronization logic is configured to; discover if one of the enabled cores of the domain sharing the resource has a target operating state less restrictive than a currently implemented power-conserving operating state; enable the core, if it is authorized to coordinate with that resource, to repeal a power-conserving operating state for the resource if the synchronization logic has discovered that an enabled core of the domain has a target operating state less restrictive than the power-conserving operating state.
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15. A decentralized, microcode-implemented method of discovering states of a multi-core processor comprising a plurality of physical processing cores, the method comprising:
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at least two cores participating in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, exchanged by the cores; wherein the method is applied to discover at least one of the following states; a composite power state for the processor; a composite power state for a domain of the processor, the domain comprising a group of cores that share a configurable resource operable to be configured, for purposes of power conservation, according to one of a plurality of configurations; a target power state of another core; a least restrictive target power state of any of a group of cores sharing a configurable resource; a most restrictive operating state that can be implemented by a core without interfering with corresponding target operating states of other cores; whether a core is enabled or disabled; how many cores of the multi-core processor are enabled; an identification of shared resources and domains of cores amongst which various configurable resources are shared; a hierarchical coordination system of the cores used for managing shared resources; an availability within the multi-core processor of sideband communication wires to coordinate cores, which sideband communication wires are independent of a system bus connecting the multi-core processor to a chipset; and a hierarchical coordination system of the cores applied to inter-core communications over sideband communication wires that are independent of a system bus connecting the multi-core processor to a chipset. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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23. A microcode routine encoded in a non-transitory computer readable storage medium of a physical core of a multi-core processor, the microcode routine comprising code for discovering an applicable state of the multi-core processor using a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, exchanged by the cores;
wherein the applicable state is one of the following states; a composite power state for the processor; a composite power state for a domain of the processor, the domain comprising a group of cores that share a configurable resource operable to be configured, for purposes of power conservation, according to one of a plurality of configurations; a target power state of another core; a least restrictive target power state of any of a group of cores sharing a configurable resource; a most restrictive operating state that can be implemented by a core without interfering with corresponding target operating states of other cores; whether a core is enabled or disabled; how many cores of the multi-core processor are enabled; an identification of shared resources and domains of cores amongst which various configurable resources are shared; a hierarchical coordination system of the cores used for managing shared resources; an availability within the multi-core processor of sideband communication wires to coordinate cores, which sideband communication wires are independent of a system bus connecting the multi-core processor to a chipset; and a hierarchical coordination system of the cores applied to inter-core communications over sideband communication wires that are independent of a system bus connecting the multi-core processor to a chipset.
Specification