Method and system for power-efficient and non-signal-degrading voltage regulation in memory subsystems

• US 8,782,452 B2
• Filed: 07/27/2009
• Issued: 07/15/2014
• Est. Priority Date: 07/27/2009
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Bacchus, Reza M., Nguyen, Vincent, Benedict, Melvin K.
• Primary Examiner(s): CONNOLLY, MARK A
• Application Number:
  US13/383,359
• Publication Number:
  US 20120110363A1
• Time in Patent Office: 1,814 Days
• Field of Search: 713/300, 713/320, 365/226, 365/227
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.

Claims

1. A memory subsystem comprising:

a memory controller;

one or more memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media; and

a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips, wherein the voltage regulators are adjustable to enable voltage outputs to be adjusted independently from other memory-subsystem components.

2. The memory subsystem of claim 1 wherein the memory modules are dual-in-line memory modules interconnected with the memory controller by a memory bus.

3. The memory subsystem of claim 1 wherein the voltage regulators are replaceable.

4. The memory subsystem of claim 1 wherein the voltage regulators are mounted to each memory-module substrate, with output from the voltage regulators routed to power-input pins of each memory chip contained in each memory module.

5. The memory subsystem of claim 1 wherein the voltage regulators are included in a discrete voltage regulation component, with output from the voltage regulators routed through memory-module sockets to power-input pins of each memory chip contained in each memory module.

6. A computer system or other electronic device that contains the memory subsystem of claim 1 as a subcomponent and that includes a system power supply that outputs the power-supply signal routed to the two or more voltage regulators.

7. The memory subsystem of claim 1 wherein the memory modules are fully-buffered dual-in-line memory modules interconnected with the memory controller by serial input and output communications media and a system-management bus.

8. The memory subsystem of claim 1 wherein the memory modules are multiple memory chips mounted to a motherboard.

9. A memory module comprising:

multiple memory chips;

a substrate to which the multiple memory chips are mounted and electronically connected to one or more communications-media interfaces; and

a power-supply signal routed to two or more voltage regulators mounted to, or fabricated within, the substrate, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips, wherein the voltage regulators are adjustable to enable voltage outputs to be adjusted independently from other memory-module components.

10. The memory module of claim 9 wherein the memory module is a dual-in-line memory module interconnected with a memory controller by a memory bus.

11. The memory module of claim 9 wherein the voltage regulators are replaceable.

12. A memory subsystem that contains the memory module of claim 9 as subcomponent.

13. A computer system or other electronic device that contains the memory subsystem of claim 12 as a subcomponent and that includes a system power supply that outputs the power-supply signal routed to the two or more voltage regulators.

14. A memory chip that accepts two or more different power signals through input power-signal pins from the voltage regulators of the memory module of claim 9.

15. The memory module of claim 9 wherein the memory module is a fully-buffered dual-in-line memory module interconnected with the memory controller by serial input and output communications media and a system-management bus.

16. A memory module comprising:

multiple memory chips;

a substrate to which the multiple memory chips are mounted and electronically connected to one or more communications-media interfaces; and

a power-supply signal routed to two or more voltage regulators mounted to, or fabricated within, the substrate, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips,

wherein the multiple memory chips accept two or more different power signals through input power-signal pins from the voltage regulators.

17. A memory subsystem that contains the memory module of claim 16 as subcomponent.

18. A computer system or other electronic device that contains the memory subsystem of claim 17 as a subcomponent and that includes a system power supply that outputs the power-supply signal routed to the two or more voltage regulators.

19. The memory module of claim 16 wherein the memory module is a dual-in-line memory module interconnected with a memory controller by a memory bus.

20. The memory module of claim 16 wherein the memory module is a fully-buffered dual-in-line memory module interconnected with the memory controller by serial input and output communications media and a system-management bus.