Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis

• US 8,782,582 B1
• Filed: 07/30/2013
• Issued: 07/15/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Atrenta Incorporated (Synopsys Incorporated)
• Inventors: Gupta, Jitendra, Varadarajan, Ravi, Dabare, Ashima, Krishna, Kshitiz, Mathur, Sanjiv
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US13/954,097
• Time in Patent Office: 350 Days
• Field of Search: 716/106
• US Class Current: 716/106
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

This invention provides a method for detecting physical implementation hot-spots in a pre-placement integrated circuit design. The method first identifies physical issues at an object level. Physical issues include timing, routing congestion, clocking, scan, power, and thermal. The method then analyzes these physical issues over a collection of connected logic cell and large cell instances and determines a physical implementation hot-spot severity based on the number and severity of physical issues as well as the number of objects in the related collection.

Claims

1. A method implemented in a computing system for analyzing physical implementation issues in a pre-placement integrated circuit design, comprising:

receiving in the system a hardware description of a pre-placement integrated circuit design;

analyzing for each logic cell in the received hardware description a set of physical issue metrics and identifying any logic cell having a value for at least one such metric exceeding a corresponding specified threshold;

measuring for each identified logic cell a physical issue severity based on the values of all metrics exceeding said corresponding thresholds, the physical issue severity for any identified logic cell being computed as a sum of normalized metric values for that logic cell;

determining any collection of identified logic cells based on proximity of the respective identified logic cells with related physical issue metrics;

analyzing for each determined collection a hotspot severity metric based on the physical issue severity of each logic cell in the collection; and

outputting a physical implementation hotspot severity report for the analyzed collections.

2. The method as in claim 1, wherein the set of physical issue metrics include any one or more of a fan-in cone (FICN) metric representing a number of primary-inputs and flip-flops that drive a logic cell in the received circuit design;

a fan-out cone (FOCN) metric representing a number of primary-outputs and flip-flops driven by a logic cell in the received circuit design;

a fan-in logic depth (FILD) metric representing a logic depth of a fan-in cone of a logic circuit in the received circuit design;

a fan-out logic depth (FOLD) metric representing a logic depth of a fan-out cone of a logic circuit in the received circuit design;

a fan-in large multiplexor (FILM) metric representing a measure of any large multiplexors in a fan-in cone of a logic circuit in the received circuit design; and

a fan-out large multiplexor (FOLM) metric representing a measure of any large multiplexors in a fan-out cone of a logic circuit in the received circuit design.

3. The method as in claim 1, wherein thresholds for each physical issue metric are user specifiable.

4. The method as in claim 1, wherein scaling factors for normalizing metric values in computing the physical issue severity are user specifiable.

5. The method as in claim 1, wherein logic cell proximity for determining membership in any collection of logic cells is a physical connection between identified logic cells in the received description of the circuit design.

10. The method as in claim 1, wherein analyzing for each determined collection a hotspot severity metric includes a filtering out of identified complementary issues between connected logic cells in a collection.

11. A computer software product containing instructions embodied as an executable program in a tangible computer-readable medium that, when executed in a computing system, perform the method of claim 1.

6. A method implemented in a computing system for analyzing physical implementation issues in a pre-placement integrated circuit design, comprising:

receiving in the system a hardware description of a pre-placement integrated circuit design;

analyzing for each logic cell in the received hardware description a set of physical issue metrics and identifying any logic cell having a value for at least one such metric exceeding a corresponding specified threshold;

measuring for each identified logic cell a physical issue severity based on the values of all metrics exceeding said corresponding thresholds;

determining any collection of identified logic cells based on proximity of the respective identified logic cells with related physical issue metrics;

analyzing for each determined collection a hotspot severity metric based on the physical issue severity of each logic cell in the collection, wherein the hotspot severity metric is computed as a sum of weighted physical severity metrics for each logic cell in a collection; and

outputting a physical implementation hotspot severity report for the analyzed collections.

7. The method as in claim 6, wherein scaling factors for the physical severity metrics are user specifiable.

8. The method as in claim 6, wherein scaling factors for the physical severity metrics are based on at least one of timing criticality and placement criticality of the logic cells in the collection.

9. The method as in claim 8, wherein timing criticality of each logic cell is determined from any one or more of logic depth, logic cell delay, fan-in, fan-out and user-specified timing constraints.

12. A computing system for analyzing physical implementation issues in a pre-placement integrated circuit design, comprising at least one processing unit and a memory accessible by the processing unit, the memory storing a hardware description of at least a portion of the circuit design, the memory also storing a set of program instructions of a physical hotspot debug tool that when executed by the processing unit causes the system to:

analyze, for each logic cell in the hardware description stored in the memory, a set of physical issue metrics and identify any logic cell having a value for at least one such metric that exceeds a corresponding specified threshold;

measure, for each identified logic cell, a physical issue severity based on the values of all metrics exceeding said corresponding thresholds, the physical issue severity for any identified logic cell being computed as a sum of normalized metric values for that logic cell;

determine any collection of identified logic cells based on proximity of the respective identified logic cells with related physical issue metrics;

analyze, for each determined collection, a hotspot severity metric based on the physical issue severity of each logic cell in the collection; and

output a physical implementation hotspot severity report for the analyzed collections.

13. A system as in claim 12, wherein the set of physical issue metrics include any one or more of a fan-in cone (FICN) metric representing a number of primary-inputs and flip-flops that drive a logic cell in the stored circuit design;

a fan-out cone (FOCN) metric representing a number of primary-outputs and flip-flops driven by a logic cell in the stored circuit design;

a fan-in logic depth (FILD) metric representing a logic depth of a fan-in cone of a logic circuit in the stored circuit design;

a fan-out logic depth (FOLD) metric representing a logic depth of a fan-out cone of a logic circuit in the stored circuit design;

a fan-in large multiplexor (FILM) metric representing a measure of any large multiplexors in a fan-in cone of a logic circuit in the stored circuit design; and

a fan-out large multiplexor (FOLM) metric representing a measure of any large multiplexors in a fan-out cone of a logic circuit in the stored circuit design.

14. The system as in claim 12, wherein thresholds for each physical issue metric are user specifiable.

15. The system as in claim 12, wherein scaling factors for normalizing metric values in computing the physical issue severity are user specifiable.

16. The system as in claim 12, wherein logic cell proximity for determining membership in any collection of logic cells is a physical connection between identified logic cells in the received description of the circuit design.

21. The system as in claim 12, wherein analyzing for each determined collection a hotspot severity metric includes a filtering out of identified complementary issues between connected logic cells in a collection.

22. The system as in claim 12 that comprises a programmable general-purpose computer system or a computer-aided design (CAD) system.

17. A computing system for analyzing physical implementation issues in a pre-placement integrated circuit design, comprising at least one processing unit and a memory accessible by the processing unit, the memory storing a hardware description of at least a portion of the circuit design, the memory also storing a set of program instructions of a physical hotspot debug tool that when executed by the processing unit causes the system to:

analyze, for each logic cell in the hardware description stored in the memory, a set of physical issue metrics and identify any logic cell having a value for at least one such metric that exceeds a corresponding specified threshold;

measure, for each identified logic cell, a physical issue severity based on the values of all metrics exceeding said corresponding thresholds;

determine any collection of identified logic cells based on proximity of the respective identified logic cells with related physical issue metrics;

analyze, for each determined collection, a hotspot severity metric based on the physical issue severity of each logic cell in the collection, wherein the hotspot severity metric is computed as a sum of weighted physical severity metrics for each logic cell in a collection; and

output a physical implementation hotspot severity report for the analyzed collections.

18. The system as in claim 17, wherein scaling factors for the physical severity metrics are user specifiable.

19. The system as in claim 17, wherein scaling factors for the physical severity metrics are based on at least one of timing criticality and placement criticality of the logic cells in the collection.

20. The system as in claim 19, wherein timing criticality of each logic cell is determined from any one or more of logic depth, logic cell delay, fan-in, fan-out and user-specified timing constraints.