Post-placement cell shifting
First Claim
1. A method for reworking a plurality of cells initially placed in a circuit design, the method comprising:
- a computer ordering the plurality of cells of a circuit design to form an inflation cell set such that each cell of the circuit design is assigned a corresponding weight calculated from an aggregate routing cost of the cell divided by a cell width of the cell, wherein the aggregate routing cost is a weighted combination of at least two of the group consisting of a count of pins in the cell, pin area cost, and a cost based on a sum for all cells of the plurality of cells of a sum for each cell of each rectangular area that encloses each pair of pins of the cell;
the computer arranging the plurality of cells by each corresponding weight, to form an ordered inflation cell set having a corresponding order;
the computer adding to a subset of cells, each cell of the ordered inflation cell set in the corresponding order, until the cells in the subset of cells, as processed by an operation, exceed a predetermined proportion of an assigned semiconductor area, wherein the operation comprises;
growing a cell to form a growth area summed to an accumulated growth, andcomparing the accumulated growth to the predetermined proportion; and
,in response to the accumulated growth exceeding the predetermined proportion;
the computer legalizing the subset of cells to form overlap-free placement of the cells in the assigned semiconductor area.
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Accused Products
Abstract
A computer implemented method for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
23 Citations
1 Claim
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1. A method for reworking a plurality of cells initially placed in a circuit design, the method comprising:
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a computer ordering the plurality of cells of a circuit design to form an inflation cell set such that each cell of the circuit design is assigned a corresponding weight calculated from an aggregate routing cost of the cell divided by a cell width of the cell, wherein the aggregate routing cost is a weighted combination of at least two of the group consisting of a count of pins in the cell, pin area cost, and a cost based on a sum for all cells of the plurality of cells of a sum for each cell of each rectangular area that encloses each pair of pins of the cell; the computer arranging the plurality of cells by each corresponding weight, to form an ordered inflation cell set having a corresponding order; the computer adding to a subset of cells, each cell of the ordered inflation cell set in the corresponding order, until the cells in the subset of cells, as processed by an operation, exceed a predetermined proportion of an assigned semiconductor area, wherein the operation comprises; growing a cell to form a growth area summed to an accumulated growth, and comparing the accumulated growth to the predetermined proportion; and
,in response to the accumulated growth exceeding the predetermined proportion;
the computer legalizing the subset of cells to form overlap-free placement of the cells in the assigned semiconductor area.
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Specification
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- Resources
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsAlpert, Charles J, Li, Zhuo D, Nam, Gi-Joon, Ramji, Shyam, Reddy, Lakshmi N, Roy, Jarrod A, Taghavi, Taraneh E, Villarrubia, Paul G, Viswanathan, Natarajan
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Primary Examiner(s)Dinh, Paul
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Application NumberUS13/902,303Publication NumberTime in Patent Office417 DaysField of Search716100-106, 716110-112, 716118-126, 716/132, 716/135US Class Current716/110CPC Class CodesG06F 30/392 Floor-planning or layout, e...
