Power managers for an integrated circuit

• US 8,782,590 B2
• Filed: 06/20/2011
• Issued: 07/15/2014
• Est. Priority Date: 05/07/2003
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Hoberman, Barry Alan, Hillman, Daniel L., Shiell, Jon
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US13/164,362
• Publication Number:
  US 20120043812A1
• Time in Patent Office: 1,121 Days
• Field of Search: 716/100, 716/126, 716/127, 716/132, 716/133
• US Class Current: 716/133
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 4/00 Circuit arrangements for mains or distribution networks not specified as ac or dc
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.

Claims

1. A system comprising:

an integrated circuit;

a plurality of power islands of the integrated circuit having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions;

a plurality of low leakage sleep circuits of the integrated circuit that are coupled to the power islands; and

a power management processor coupled to each of the low leakage sleep circuits, the power management processor being dedicated to execute power management software to individually control each of the power consumptions, and the power management processor being configured to;

a) monitor the power consumption signals; and

b) change power consumption in at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

ii) choosing a frequency of operation of the at least one of the power islands.

2. The system of claim 1 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to a respective one of the power islands.

3. The system of claim 2 wherein each of the low leakage sleep circuits modifies the supply voltage to a respective one of the power islands during a power down mode.

4. The system of claim 1 wherein the power consumption signal of each of the power islands includes temperature measurement.

5. The system of claim 1 wherein the power consumption signal of each of the power islands includes power dissipation measurement.

6. The system of claim 1 wherein the power consumption signal of the at least one of the power islands includes temperature measurement.

7. The system of claim 1 wherein the power consumption signal of the at least one of the power islands includes power dissipation measurement.

8. A processor implemented method comprising:

employing a power management processor that is dedicated to execute power management software to individually control each of power consumptions of a plurality of power islands of an integrated circuit, each power island of the power islands having a power consumption signal indicating a respective one of the power consumptions, and the employing the power management processor including monitoring the power consumption signals; and

changing power consumption in at least one of the power islands by the power management processor;

a) changing a supply voltage by controlling at least one of low leakage sleep circuits of the integrated circuit, and b) choosing a frequency of operation of the at least one of the power islands.

9. A system comprising:

an integrated circuit;

a plurality of power islands of the integrated circuit having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions;

a plurality of low leakage sleep circuits of the integrated circuit that are coupled to at least one of the power islands; and

a power management processor coupled to each of the low leakage sleep circuits, the power management processor being dedicated to execute power management software to individually control each of the power consumptions, and the power management processor being configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

ii) choosing a frequency of operation of the at least one of the power islands.

10. The system of claim 9 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to the at least one of the power islands.

11. The system of claim 10 wherein each of the low leakage sleep circuits modifies the supply voltage to the at least one of the power islands during a power down mode.

12. The system of claim 9 wherein the power consumption signal of each of the power islands includes temperature measurement.

13. The system of claim 9 wherein the power consumption signal of each of the power islands includes power dissipation measurement.

14. The system of claim 9 wherein the power consumption signal of the at least one of the power islands includes temperature measurement.

15. The system of claim 9 wherein the power consumption signal of the at least one of the power islands includes power dissipation measurement.

16. A system comprising:

an integrated circuit;

a plurality of power islands of the integrated circuit having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions;

a plurality of low leakage sleep circuits of the integrated circuit that are coupled to the power islands; and

a power manager coupled to each of the low leakage sleep circuits, the power manager being configured to individually control each of the power consumptions, and the power manager being further configured to;

a) monitor the power consumption signals; and

b) change power consumption in at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

ii) choosing a frequency of operation of the at least one of the power islands.

17. The system of claim 16 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to a respective one of the power islands.

18. The system of claim 17 wherein each of the low leakage sleep circuits modifies the supply voltage to a respective one of the power islands during a power down mode.

19. The system of claim 16 wherein the power consumption signal of each of the power islands includes temperature measurement.

20. The system of claim 16 wherein the power consumption signal of each of the power islands includes power dissipation measurement.

21. The system of claim 16 wherein the power consumption signal of the at least one of the power islands includes temperature measurement.

22. The system of claim 16 wherein the power consumption signal of the at least one of the power islands includes power dissipation measurement.

23. A system comprising:

an integrated circuit;

a plurality of power islands of the integrated circuit having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions;

a plurality of low leakage sleep circuits of the integrated circuit that are coupled to at least one of the power islands; and

a power manager coupled to each of the low leakage sleep circuits, the power manager being configured to individually control each of the power consumptions, and the power manager being further configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

ii) choosing a frequency of operation of the at least one of the power islands.

24. The system of claim 23 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to the at least one of the power islands.

25. The system of claim 24 wherein each of the low leakage sleep circuits modifies the supply voltage to the at least one of the power islands during a power down mode.

26. The system of claim 23 wherein the power consumption signal of each of the power islands includes temperature measurement.

27. The system of claim 23 wherein the power consumption signal of each of the power islands includes power dissipation measurement.

28. The system of claim 23 wherein the power consumption signal of the at least one of the power islands includes temperature measurement.

29. The system of claim 23 wherein the power consumption signal of the at least one of the power islands includes power dissipation measurement.

30. An integrated circuit comprising:

an integrated circuit chip;

a plurality of power islands disposed on the integrated circuit chip having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions;

a plurality of low leakage sleep circuits disposed on the integrated circuit chip, the low leakage sleep circuits being coupled to the power islands; and

a power management processor coupled to each of the low leakage sleep circuits, the power management processor being disposed on the integrated circuit chip and being dedicated to execute power management software to individually control each of the power consumptions, and the power management processor being configured to;

a) monitor the power consumption signals; and

b) change power consumption in at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

ii) choosing a frequency of operation of the at least one of the power islands.

31. The integrated circuit of claim 30 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to a respective one of the power islands.

32. The integrated circuit of claim 31 wherein each of the low leakage sleep circuits modifies the supply voltage to a respective one of the power islands during a power down mode.

33. The integrated circuit of claim 30 wherein the power consumption signal of each of the power islands includes temperature measurement.

34. The integrated circuit of claim 30 wherein the power consumption signal of each of the power islands includes power dissipation measurement.

35. The integrated circuit of claim 30 wherein the power consumption signal of the at least one of the power islands includes temperature measurement.

36. The integrated circuit of claim 30 wherein the power consumption signal of the at least one of the power islands includes power dissipation measurement.

37. An integrated circuit comprising:

an integrated circuit chip;

a plurality of power islands disposed on the integrated circuit chip having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions;

a plurality of low leakage sleep circuits disposed on the integrated circuit chip, the low leakage sleep circuits being coupled to at least one of the power islands; and

a power management processor coupled to each of the low leakage sleep circuits, the power management processor being disposed on the integrated circuit chip and being dedicated to execute power management software to individually control each of the power consumptions, and the power management processor being configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

ii) choosing a frequency of operation of the at least one of the power islands.

38. The integrated circuit of claim 37 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to the at least one of the power islands.

39. The integrated circuit of claim 38 wherein each of the low leakage sleep circuits modifies the supply voltage to the at least one of the power islands during a power down mode.

40. The integrated circuit of claim 37 wherein the power consumption signal of each of the power islands includes temperature measurement.

41. The integrated circuit of claim 37 wherein the power consumption signal of each of the power islands includes power dissipation measurement.

42. The integrated circuit of claim 37 wherein the power consumption signal of the at least one of the power islands includes temperature measurement.

43. The integrated circuit of claim 37 wherein the power consumption signal of the at least one of the power islands includes power dissipation measurement.

44. An integrated circuit comprising:

an integrated circuit chip;

a plurality of power islands disposed on the integrated circuit chip having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions;

a plurality of low leakage sleep circuits disposed on the integrated circuit chip, the low leakage sleep circuits being coupled to the power islands; and

a power manager coupled to each of the low leakage sleep circuits, the power manager being disposed on the integrated circuit chip and being configured to individually control each of the power consumptions, and the power manager being further configured to;

a) monitor the power consumption signals; and

b) change power consumption in at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

ii) choosing a frequency of operation of the at least one of the power islands.

45. The integrated circuit of claim 44 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to a respective one of the power islands.

46. The integrated circuit of claim 45 wherein each of the low leakage sleep circuits modifies the supply voltage to a respective one of the power islands during a power down mode.

47. The integrated circuit of claim 44 wherein the power consumption signal of each of the power islands includes temperature measurement.

48. The integrated circuit of claim 44 wherein the power consumption signal of each of the power islands includes power dissipation measurement.

49. The integrated circuit of claim 44 wherein the power consumption signal of the at least one of the power islands includes temperature measurement.

50. The integrated circuit of claim 44 wherein the power consumption signal of the at least one of the power islands includes power dissipation measurement.

51. An integrated circuit comprising:

an integrated circuit chip;

a plurality of power islands disposed on the integrated circuit chip having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions;

a plurality of low leakage sleep circuits disposed on the integrated circuit chip, the low leakage sleep circuits being coupled to at least one of the power islands; and

a power manager coupled to each of the low leakage sleep circuits, the power manager being disposed on the integrated circuit chip and being configured to individually control each of the power consumptions, and the power manager being further configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

ii) choosing a frequency of operation of the at least one of the power islands.

52. The integrated circuit of claim 51 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to the at least one of the power islands.

53. The integrated circuit of claim 52 wherein each of the low leakage sleep circuits modifies the supply voltage to the at least one of the power islands during a power down mode.

54. The integrated circuit of claim 51 wherein the power consumption signal of each of the power islands includes temperature measurement.

55. The integrated circuit of claim 51 wherein the power consumption signal of each of the power islands includes power dissipation measurement.

56. The integrated circuit of claim 51 wherein the power consumption signal of the at least one of the power islands includes temperature measurement.

57. The integrated circuit of claim 51 wherein the power consumption signal of the at least one of the power islands includes power dissipation measurement.

58. A system comprising:

an integrated circuit;

a plurality of power islands of the integrated circuit having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions, and at least one of the power islands including a low power memory block;

a plurality of low leakage sleep circuits of the integrated circuit that are coupled to the power islands; and

a power management processor coupled to each of the low leakage sleep circuits, the power management processor being dedicated to execute power management software to individually control each of the power consumptions, and the power management processor being configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

iii) choosing a frequency of operation of the at least one of the power islands.

59. The system of claim 58 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to a respective one of the power islands.

60. A system comprising:

an integrated circuit;

a plurality of power islands of the integrated circuit having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions, and at least one of the power islands including a low power memory block;

a plurality of low leakage sleep circuits of the integrated circuit that are coupled to the at least one of the power islands; and

a power management processor coupled to each of the low leakage sleep circuits, the power management processor being dedicated to execute power management software to individually control each of the power consumptions, and the power management processor being configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

iii) choosing a frequency of operation of the at least one of the power islands.

61. The system of claim 60 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to the at least one of the power islands.

62. A system comprising:

an integrated circuit;

a plurality of power islands of the integrated circuit having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions, and at least one of the power islands including a low power memory block;

a plurality of low leakage sleep circuits of the integrated circuit that are coupled to the power islands; and

a power manager coupled to each of the low leakage sleep circuits, the power manager being configured to individually control each of the power consumptions, and the power manager being further configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

iii) choosing a frequency of operation of the at least one of the power islands.

63. The system of claim 62 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to a respective one of the power islands.

64. A system comprising:

an integrated circuit;

a plurality of power islands of the integrated circuit having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions, and at least one of the power islands including a low power memory block;

a plurality of low leakage sleep circuits of the integrated circuit that are coupled to the at least one of the power islands; and

a power manager coupled to each of the low leakage sleep circuits, the power manager being configured to individually control each of the power consumptions, and the power manager being further configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

iii) choosing a frequency of operation of the at least one of the power islands.

65. The system of claim 64 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to the at least one of the power islands.

66. An integrated circuit comprising:

an integrated circuit chip;

a plurality of power islands disposed on the integrated circuit chip having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions, and at least one of the power islands including a low power memory block;

a plurality of low leakage sleep circuits disposed on the integrated circuit chip, the low leakage sleep circuits being coupled to the power islands; and

a power management processor coupled to each of the low leakage sleep circuits, the power management processor being disposed on the integrated circuit chip and being dedicated to execute power management software to individually control each of the power consumptions, and the power management processor being configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

iii) choosing a frequency of operation of the at least one of the power islands.

67. The integrated circuit of claim 66 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to a respective one of the power islands.

71. The integrated circuit of claim 66 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to a respective one of the power islands.

68. An integrated circuit comprising:

an integrated circuit chip;

a plurality of power islands disposed on the integrated circuit chip having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions, and at least one of the power islands including a low power memory block;

a plurality of low leakage sleep circuits disposed on the integrated circuit chip, the low leakage sleep circuits being coupled to the at least one of the power islands; and

a power management processor coupled to each of the low leakage sleep circuits, the power management processor being disposed on the integrated circuit chip and being dedicated to execute power management software to individually control each of the power consumptions, and the power management processor being configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

iii) choosing a frequency of operation of the at least one of the power islands.

69. The integrated circuit of claim 68 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to the at least one of the power islands.

70. An integrated circuit comprising:

an integrated circuit chip;

a plurality of power islands disposed on the integrated circuit chip having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions, and at least one of the power islands including a low power memory block;

a plurality of low leakage sleep circuits disposed on the integrated circuit chip, the low leakage sleep circuits being coupled to the power islands; and

a power manager coupled to each of the low leakage sleep circuits, the power manager being disposed on the integrated circuit chip and being configured to individually control each of the power consumptions, and the power manager being further configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

iii) choosing a frequency of operation of the at least one of the power islands.

72. An integrated circuit comprising:

an integrated circuit chip;

a plurality of power islands disposed on the integrated circuit chip having associated power consumptions, each of the power islands having a power consumption signal indicating a respective one of the power consumptions, and at least one of the power islands including a low power memory block;

a plurality of low leakage sleep circuits disposed on the integrated circuit chip, the low leakage sleep circuits being coupled to the at least one of the power islands; and

a power manager coupled to each of the low leakage sleep circuits, the power manager being disposed on the integrated circuit chip and being configured to individually control each of the power consumptions, and the power manager being further configured to;

a) monitor the power consumption signals; and

b) change power consumption in the at least one of the power islands by;

i) changing a supply voltage by controlling at least one of the low leakage sleep circuits; and

iii) choosing a frequency of operation of the at least one of the power islands.

73. The integrated circuit of claim 72 wherein each of the low leakage sleep circuits is connected in series to a source of the supply voltage and to the at least one of the power islands.