Semiconductor device and manufacturing method thereof

• US 8,785,266 B2
• Filed: 01/09/2012
• Issued: 07/22/2014
• Est. Priority Date: 01/12/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US13/345,940
• Publication Number:
  US 20120175609A1
• Time in Patent Office: 925 Days
• Field of Search: 257/1, 257/8, 257/43, 257/49, 257/57, 257/66, 257/288, 257/327, 257/353, 257/618, 257/E21.006, 438/85, 438/104, 438/149, 438/151, 438/164, 438/166, 438/197, 438/412, 438/479, 438/478, 438/502, 438/509
• US Class Current: 438/164
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors

Abstract

A first oxide insulating film is formed over a substrate. After a first oxide semiconductor film is formed over the first oxide insulating film, heat treatment is performed, so that hydrogen contained in the first oxide semiconductor film is released and part of oxygen contained in the first oxide insulating film is diffused into the first oxide semiconductor film. Thus, a second oxide semiconductor film with reduced hydrogen concentration and reduced oxygen defect is formed. Then, the second oxide semiconductor film is selectively etched to form a third oxide semiconductor film, and a second oxide insulating film is formed. The second oxide insulating film is selectively etched and a protective film covering an end portion of the third oxide semiconductor film is formed. Then, a pair of electrodes, a gate insulating film, and a gate electrode are formed over the third oxide semiconductor film and the protective film.

Claims

1. A method for manufacturing a semiconductor device, comprising steps of:

forming a first oxide insulating film over a substrate;

forming an oxide semiconductor film over the first oxide insulating film;

performing heat treatment to the oxide semiconductor film;

selectively etching the oxide semiconductor film to have an end portion of the oxide semiconductor film, wherein the end portion of the oxide semiconductor film comprises a side surface and a top surface of the oxide semiconductor film;

forming a second oxide insulating film over the oxide semiconductor film;

selectively etching the second oxide insulating film, thereby forming a protective film covering the end portion of the oxide semiconductor film;

forming a pair of wirings in direct contact with the protective film and the oxide semiconductor film;

forming a gate insulating film in direct contact with the top surface of the oxide semiconductor film after forming the protective film; and

forming a gate electrode overlapping with the oxide semiconductor film over the gate insulating film.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of:

adding a dopant to the oxide semiconductor film after forming the gate electrode, so that a first oxide semiconductor region overlapping with the gate electrode, a pair of second oxide semiconductor regions between which the first oxide semiconductor region is sandwiched, and a pair of third oxide semiconductor regions which overlaps with the pair of wirings and between which the pair of second oxide semiconductor regions is sandwiched are formed.

3. The method for manufacturing a semiconductor device according to claim 2,

wherein the pair of second oxide semiconductor regions is regions containing the dopant, and

wherein the dopant is at least one of nitrogen, phosphorus, arsenic, hydrogen, helium, neon, argon, krypton, and xenon.

4. The method for manufacturing a semiconductor device according to claim 1, wherein an oxide insulating film from which part of oxygen is released by heat treatment is formed as the first oxide insulating film and the second oxide insulating film.

5. The method for manufacturing a semiconductor device according to claim 1, wherein an oxide insulating film containing oxygen at a proportion exceeding a stoichiometric proportion is formed as the first oxide insulating film and the second oxide insulating film.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed at a temperature higher than or equal to 150°

C. and lower than a strain point of the substrate.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor film includes at least one element selected from In, Ga, Sn, and Zn.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed at a temperature at which hydrogen is released from the oxide semiconductor film and oxygen contained in the first oxide insulating film is diffused into the oxide semiconductor film.

9. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed at a temperature at which hydrogen is released from the oxide semiconductor film and oxygen contained in the first oxide insulating film and the second oxide insulating film is diffused into the oxide semiconductor film.

10. The method for manufacturing a semiconductor device according to claim 1, wherein the gate insulating film is formed to be in direct contact with top surfaces of the pair of wirings.

11. A method for manufacturing a semiconductor device, comprising steps of:

forming a first oxide insulating film over a substrate;

forming an oxide semiconductor film over the first oxide insulating film;

performing heat treatment to the oxide semiconductor film;

selectively etching the oxide semiconductor film to have an end portion of the oxide semiconductor film;

forming a second oxide insulating film over the oxide semiconductor film;

selectively etching the second oxide insulating film, thereby forming a protective film covering the end portion of the oxide semiconductor film, wherein the end portion of the oxide semiconductor film comprises a side surface and a top surface of the oxide semiconductor film;

forming a pair of wirings in direct contact with the protective film and the oxide semiconductor film;

forming a gate insulating film in direct contact with the top surface of the oxide semiconductor film after forming the protective film; and

forming a gate electrode overlapping with the oxide semiconductor film over the gate insulating film,

wherein the step of selectively etching the oxide semiconductor film is performed after the step of performing heat treatment.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising a step of:

adding a dopant to the oxide semiconductor film after forming the gate electrode, so that a first oxide semiconductor region overlapping with the gate electrode, a pair of second oxide semiconductor regions between which the first oxide semiconductor region is sandwiched, and a pair of third oxide semiconductor regions which overlaps with the pair of wirings and between which the pair of second oxide semiconductor regions is sandwiched are formed.

13. The method for manufacturing a semiconductor device according to claim 12,

wherein the pair of second oxide semiconductor regions is regions containing the dopant, and

wherein the dopant is at least one of nitrogen, phosphorus, arsenic, hydrogen, helium, neon, argon, krypton, and xenon.

14. The method for manufacturing a semiconductor device according to claim 11, wherein an oxide insulating film from which part of oxygen is released by heat treatment is formed as the first oxide insulating film and the second oxide insulating film.

15. The method for manufacturing a semiconductor device according to claim 11, wherein an oxide insulating film containing oxygen at a proportion exceeding a stoichiometric proportion is formed as the first oxide insulating film and the second oxide insulating film.

16. The method for manufacturing a semiconductor device according to claim 11, wherein the heat treatment is performed at a temperature higher than or equal to 150°

C. and lower than a strain point of the substrate.

17. The method for manufacturing a semiconductor device according to claim 11, wherein the oxide semiconductor film includes at least one element selected from In, Ga, Sn, and Zn.

18. The method for manufacturing a semiconductor device according to claim 11, wherein the heat treatment is performed at a temperature at which hydrogen is released from the oxide semiconductor film and oxygen contained in the first oxide insulating film is diffused into the oxide semiconductor film.

19. The method for manufacturing a semiconductor device, according to claim 11, further comprising a step of:

selectively etching the second oxide insulating film, thereby forming a third oxide insulating film having a pair of openings, before forming the protective film,

wherein the pair of wirings is formed in direct contact with the third oxide insulating film having the pair of openings and the oxide semiconductor film.

20. The method for manufacturing a semiconductor device according to claim 11, wherein the gate insulating film is formed to be in direct contact with top surfaces of the pair of wirings.

21. A method for manufacturing a semiconductor device, comprising steps of:

forming a first oxide insulating film over a substrate;

forming an oxide semiconductor film over the first oxide insulating film;

performing heat treatment to the oxide semiconductor film;

selectively etching the oxide semiconductor film to have an end portion of the oxide semiconductor film;

forming a second oxide insulating film over the oxide semiconductor film;

selectively etching the second oxide insulating film, thereby forming a protective film covering the end portion of the oxide semiconductor film, wherein the end portion of the oxide semiconductor film comprises a side surface and a top surface of the oxide semiconductor film;

forming a pair of wirings in direct contact with the protective film and the oxide semiconductor film;

forming a gate insulating film in direct contact with the top surface of the oxide semiconductor film after forming the protective film; and

forming a gate electrode overlapping with the oxide semiconductor film over the gate insulating film,

wherein the step of performing heat treatment is performed after the step of selectively etching the oxide semiconductor film.

22. The method for manufacturing a semiconductor device according to claim 21, further comprising a step of:

adding a dopant to the oxide semiconductor film after forming the gate electrode, so that a first oxide semiconductor region overlapping with the gate electrode, a pair of second oxide semiconductor regions between which the first oxide semiconductor region is sandwiched, and a pair of third oxide semiconductor regions which overlaps with the pair of wirings and between which the pair of second oxide semiconductor regions is sandwiched are formed.

23. The method for manufacturing a semiconductor device according to claim 22,

wherein the pair of second oxide semiconductor regions is regions containing the dopant, and

wherein the dopant is at least one of nitrogen, phosphorus, arsenic, hydrogen, helium, neon, argon, krypton, and xenon.

24. The method for manufacturing a semiconductor device according to claim 21, wherein an oxide insulating film from which part of oxygen is released by heat treatment is formed as the first oxide insulating film and the second oxide insulating film.

25. The method for manufacturing a semiconductor device according to claim 21, wherein an oxide insulating film containing oxygen at a proportion exceeding a stoichiometric proportion is formed as the first oxide insulating film and the second oxide insulating film.

26. The method for manufacturing a semiconductor device according to claim 21, wherein the heat treatment is performed at a temperature higher than or equal to 150°

C. and lower than a strain point of the substrate.

27. The method for manufacturing a semiconductor device according to claim 21, wherein the oxide semiconductor film includes at least one element selected from In, Ga, Sn, and Zn.

28. The method for manufacturing a semiconductor device according to claim 21, wherein the heat treatment is performed at a temperature at which hydrogen is released from the oxide semiconductor film and oxygen contained in the first oxide insulating film and the second oxide insulating film is diffused into the oxide semiconductor film.

29. The method for manufacturing a semiconductor device, according to claim 21, further comprising a step of:

selectively etching the second oxide insulating film, thereby forming a third oxide insulating film having a pair of openings, before forming the protective film,

wherein the pair of wirings is formed in direct contact with the third oxide insulating film having the pair of openings and the oxide semiconductor film.

30. The method for manufacturing a semiconductor device according to claim 21, wherein the gate insulating film is formed to be in direct contact with top surfaces of the pair of wirings.