Integrating schottky diode into power MOSFET

• US 8,785,270 B2
• Filed: 07/23/2013
• Issued: 07/22/2014
• Est. Priority Date: 05/02/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Su, Yi, Ng, Daniel, Bhalla, Anup, Chang, Hong, Kim, Jongoh, Chen, John
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Schoenholtz, Joseph
• Application Number:
  US13/948,988
• Publication Number:
  US 20130309823A1
• Time in Patent Office: 364 Days
• Field of Search: None
• US Class Current: 438/237
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0891 of field-effect transistors with Schottky gate
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/782 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

Claims

1. A method for fabricating a semiconductor device, comprising:

a) forming a plurality of trenches on a substrate using a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and shield electrode pickup trenches located in a termination area outside an active area containing the active gate trenches, the gate runner/termination trenches including one or more trenches that define a mesa located in an area outside an active area containing the active gate trenches;

forming asymmetric sidewalls in the one or more trenches that define the mesa, wherein forming asymmetric sidewalls includes undercut etching a portion of an oxide layer that is at least in part covered by the second mask;

b) forming a first conductive region in the one or more trenches that define the mesa;

c) forming an intermediate dielectric region and a termination protection region in the one or more trenches that define the mesa using a second mask;

d) forming a second conductive region in the one or more trenches that define the mesa;

e) forming a first electrical contact to the second conductive regions, forming a second electrical contact to the first conductive region in the shield electrode pickup trenches located in the termination area, and forming one or more Schottky diodes within a mesa formed between termination trenches in an area outside an active area containing the active gate trenches using a third mask.

2. The method of claim 1, further comprising:

f) disposing a metal layer on the device; and

g) forming a source metal region and a gate metal region from the metal layer using a fourth mask.

3. The method of claim 1, wherein the asymmetric sidewalls include a first sidewall and a second sidewall, and the first sidewall having a thicker oxide layer than the second sidewall, the first sidewall being closer to the one or more Schottky diodes.

4. The method of claim 1, wherein forming one or more Schottky diodes includes depositing barrier metal on an exposed surface of the mesa formed between termination trenches.

5. The method of claim 4, wherein the exposed surface of the mesa is an exposed surface of a well formed within the mesa.

6. A method for fabricating a semiconductor device, comprising:

a) forming a plurality of trenches on a substrate using a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and shield electrode pickup trenches located in a termination area outside an active area containing the active gate trenches, the gate runner/termination trenches including one or more trenches that define a mesa located in an area outside an active area containing the active gate trenches;

b) forming a first conductive region in the one or more trenches that define the mesa;

c) forming an intermediate dielectric region and a termination protection region in the one or more trenches that define the mesa using a second mask;

d) forming a second conductive region in the one or more trenches that define the mesa;

e) forming a first electrical contact to the second conductive regions, forming a second electrical contact to the first conductive region in the shield electrode pickup trenches located in the termination area, and forming one or more Schottky diodes within a mesa formed between termination trenches in an area outside an active area containing the active gate trenches using a third mask;

wherein forming a Schottky diode includes performing a deep pocket implant to form a doped shielding region below a Schottky junction associated with the Schottky diode.