Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact

• US 8,785,278 B2
• Filed: 02/02/2012
• Issued: 07/22/2014
• Est. Priority Date: 02/02/2012
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Yilmaz, Hamza, Ng, Daniel, Calafut, Daniel, Bobde, Madhur, Bhalla, Anup, Pan, Ji, Lee, Yeeheng, Kim, Jongoh
• Primary Examiner(s): SANDVIK, BENJAMIN P
• Application Number:
  US13/364,948
• Publication Number:
  US 20130200451A1
• Time in Patent Office: 901 Days
• Field of Search: 257330-334
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

Claims

1. A method for manufacturing a semiconductor power device, comprising:

forming one or more trenches in a lightly doped layer of a first conductivity type on top of a heavily doped layer of the first conductivity type;

forming one or more electrically insulated gate electrodes in the one or more trenches, wherein each of the one or more trenches has a depth that extends in a first dimension, a width that extends in a second dimension and a length that extends in a third dimension, wherein the first dimension is perpendicular to a plane of the heavily doped layer and wherein the second and third dimensions are parallel to the plane of the heavily doped layer;

forming a doped body region adjacent to one or more of the trenches proximate an upper surface of the lightly doped layer, wherein the body region is of a second conductivity type that is opposite to the first conductivity type;

forming a source region proximate the upper surface and adjacent to one or more of the one or more trenches, wherein the source region includes a first heavily doped source region of the first conductivity type formed proximate the upper surface extending from a side wall of a first of the one or more trenches to a side wall of a second of the one or more trenches adjacent the first trench and a second heavily doped source region of the first conductivity type adjacent to the side wall of the first trench extending along the third dimension;

forming one or more doped implant shield regions in the lightly doped layer adjacent a bottom portion of one or more of the trenches extending along the third dimension, wherein the one or more doped implant shield regions are of the second conductivity type; and

forming one or more deep heavily doped contacts at one or more locations proximate one or more of the trenches along the third dimension, wherein the one or more deep heavily doped contacts extend in the first direction into the lightly doped layer and extend across an entire width between two adjacent trenches, wherein the one or more deep heavily doped contacts are in electrical contact with the source region, wherein forming the one or more deep heavily doped contacts further includes forming one or more deep implant regions of the second conductivity type deeper than the one or more deep heavily doped contacts, wherein the one or more deep implant regions intersect the doped implant shield region.

2. The method of claim 1, wherein forming the one or more deep heavily doped contacts includes etching through at least the first heavily doped source region to form one or more openings, implanting a dopant of the second conductivity type through a bottom of the openings thus forming one or more heavily doped contact regions on top of the one or more deep implant regions.

3. The method of claim 1, further comprising etching through at least the first heavily doped source region to form one or more openings, implanting a dopant of the second conductivity type through a bottom of the openings thus forming one or more heavily doped contact regions, filling the openings with a conductive material to form an electrical contact between at least one of the one or more deep heavily doped contacts and a source metal that is in electrical contact with the source region.

4. The method of claim 1, further comprises forming a heavily doped region of the second conductivity type under the first heavily doped source region to a depth shallower than the second heavily doped source region.

5. The method of claim 1, further comprising forming a thick bottom insulator in a bottom portion of one or more of the trenches between the gate electrode and the lightly doped layer.

6. The method of claim 1, wherein forming the source region includes forming a lightly doped region of the first conductivity type under the second heavily doped region of the first conductivity type adjacent to the side wall of the first trench extending along the third dimension.

7. The method of claim 1, further comprising forming one or more shield electrodes in one or more of the one or more trenches proximate a corresponding one or more of the one or more gate electrodes and electrically coupling the one or more shield electrodes to the source region.

8. A method for manufacturing a semiconductor power device, comprising:

forming one or more trenches in a lightly doped layer of a first conductivity type on top of a heavily doped layer of the first conductivity type;

forming one or more electrically insulated gate electrodes in the one or more trenches, wherein each of the one or more trenches has a depth that extends in a first dimension, a width that extends in a second dimension and a length that extends in a third dimension, wherein the first dimension is perpendicular to a plane of the heavily doped layer and wherein the second and third dimensions are parallel to the plane of the heavily doped layer;

forming a doped body region adjacent to one or more of the trenches proximate an upper surface of the lightly doped layer, wherein the body region is of a second conductivity type that is opposite to the first conductivity type;

forming one or more doped implant shield regions in the lightly doped layer adjacent a bottom portion of one or more of the trenches extending along the third dimension, wherein the one or more doped implant shield regions are of the second conductivity type;

forming a source region proximate the upper surface and adjacent to one or more of the trenches, wherein the source region is heavily doped of the first conductivity type;

forming one or more deep heavily doped contacts at one or more locations proximate one or more of the trenches along the third dimension, wherein the one or more deep heavily doped contacts extend in the first direction from the upper surface into the lightly doped layer and extend across an entire width between two adjacent trenches, wherein the one or more deep heavily doped contacts are in electrical contact with the source region;

forming an elongated opening in the source region in a mesa adjacent one or more of the one or more trenches, wherein a portion of the doped body region in the opening is exposed from the source region; and

forming an active cell contact in the elongated opening in the mesa wherein the active cell contact is in electrical contact with one or more of the one or more deep heavily doped contacts, wherein forming the one or more deep heavily doped contacts includes forming one or more deep implant regions of the second conductivity type deeper than the one or more deep heavily doped contacts, wherein the one or more deep implant regions intersect the doped implant shield region.

9. The method of claim 8, wherein forming the one or more deep heavily doped contacts further includes etching through at least the source region to form one or more openings, implanting a dopant of the second conductivity type through a bottom of the openings forming one or more heavily doped contact regions on top of the one or more deep implant regions, wherein the one or more heavily doped contact regions are of the second conductivity.

10. The method of claim 8, further comprising etching through at least the source region to form one or more openings, implanting a dopant of the second conductivity type through a bottom of the openings thus forming one or more heavily doped contact regions, filling the openings with a dielectric material.

11. The method of claim 10, wherein forming the elongated opening in the source region further comprising etching through the source region an elongated opening running across and having a width narrower than the one or more openings filled with dielectric material.

12. The method of claim 8, further comprising forming a thick bottom insulator in a bottom portion of one or more of the trenches between the gate electrode and the lightly doped layer.

13. The method of claim 8, further comprising forming one or more shield electrodes in one or more of the one or more trenches proximate a corresponding one or more of the one or more gate electrodes and electrically coupling the one or more shield electrodes to the source region.

14. A method for manufacturing a semiconductor power device, comprising:

forming one or more trenches in a lightly doped layer of a first conductivity type on top of a heavily doped layer of the first conductivity type;

forming one or more electrically insulated gate electrodes in the one or more trenches with a top surface of the gate electrode etched back to a level below the upper surface of the lightly doped layer, wherein each of the one or more trenches has a depth that extends in a first dimension, a width that extends in a second dimension and a length that extends in a third dimension, wherein the first dimension is perpendicular to a plane of the heavily doped layer and wherein the second and third dimensions are parallel to the plane of the heavily doped layer;

etching back the lightly doped layer to a level below the top surface of the gate electrode;

forming a doped body region adjacent to one or more of the trenches proximate an upper surface of the etched lightly doped layer, wherein the body region is of a second conductivity type opposite to the first conductivity type;

forming one or more deep heavily doped contacts at one or more locations proximate one or more of the trenches along the third dimension, wherein the one or more deep heavily doped contacts extend in the first direction from the upper surface into the lightly doped layer and extend across an entire width between two adjacent trenches; and

forming a Schottky contact in a mesa adjacent one or more of the one or more trenches, wherein the one or more deep heavily doped contacts are in electrical contact with the Schottky contact.

15. The method of claim 14, further comprising forming one or more doped implant shield regions in the lightly doped layer adjacent a bottom portion of one or more of the trenches extending along the third dimension, wherein the one or more doped implant shield regions are of the second conductivity type.

16. The method of claim 15, wherein forming the one or more deep heavily doped contacts includes forming one or more deep implant regions of the second conductivity type deeper than the heavily doped contacts, wherein the one or more deep implant regions intersect the doped implant shield region.

17. The method of claim 14, wherein forming the one or more deep heavily doped contacts includes forming the one or more deep heavily doped contacts between two adjacent trenches of the one or more trenches.

18. The method of claim 17, further comprises depositing a conductive material filling a space above the Schottky contact between the two adjacent trenches.

19. The method of claim 14, further comprising forming a thick bottom insulator in a bottom portion of one or more of the trenches between the gate electrode and the lightly doped layer.

20. The method of claim 14, wherein forming the Schottky contact includes forming a Schottky lightly doped region on top of the body region and forming a Schottky metal layer on top of the Schottky lightly doped region, wherein the Schottky lightly doped region is sandwiched between the Schottky metal layer and the body region and wherein the Schottky lightly doped region is of the second conductivity type but is less heavily doped than the body region.

21. The method of claim 14, further comprising forming one or more shield electrodes in one or more of the one or more trenches proximate a corresponding one or more of the one or more gate electrodes and electrically coupling the one or more shield electrodes to the source region.