High voltage field balance metal oxide field effect transistor (FBM)

• US 8,785,279 B2
• Filed: 07/30/2012
• Issued: 07/22/2014
• Est. Priority Date: 07/30/2012
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Yilmaz, Hamza, Bobde, Madhur, Guan, Lingpeng, Hu, Jun, Kim, Jongoh, Ding, Yongping
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US13/561,523
• Publication Number:
  US 20140027841A1
• Time in Patent Office: 722 Days
• Field of Search: 438/137, 438/138, 438/140, 257/E21.419
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A method of manufacturing a semiconductor device, comprising:

a) providing a semiconductor substrate of a first conductivity type;

b) forming an epitaxial layer of the first conductivity type on a top surface of the semiconductor substrate, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped;

c) forming body regions of a second conductivity type that is opposite of the first conductivity type near the top surface of the surface shielded region;

d) forming source regions of the first conductivity type near the top surface of the surface shielded region;

e) forming a plurality of gates on the top surface of the surface shielded region;

f) forming a drain on a bottom surface of the semiconductor substrate;

g) forming a plurality of trenches in the surface shielded region, wherein the trenches are lined with a trench insulation material and filled with an electrically conductive trench filling material configured to be in electrical contact with a source electrode on top of the surface shielded region and in electrical contact with the source region;

h) forming a plurality of buried doped regions of the second conductivity type, whereby each is positioned below one of the plurality of trenches, and wherein the buried doped regions extend to a depth substantially the same as the bottom surface of the surface shielded region; and

i) forming one or more charge linking paths of the second conductivity type along one or more trench walls of the plurality of trenches and configured to electrically connect a buried doped region to the body region.

2. The method of claim 1, wherein the surface shielded region is configured to support approximately one-third of the breakdown voltage (BV) and the voltage blocking region is configured to support approximately two-thirds of the BV.

3. The method of claim 2, wherein the buried doped region is configured to support approximately one-half of the BV supported by the surface shielded region and the trench insulation material supports the remainder of the BV supported by the surface shielded region.

4. The method of claim 1, wherein the trench filling material in some of the trenches is insulated from the source electrode and is electrically connected to the gate electrode.

5. The method of claim 1, wherein a doping concentration of the surface shielded region is between 5 and 100 times greater than a doping concentration of the voltage blocking region.

6. The method of claim 1, wherein the trench filling material is polysilicon.

7. The method of claim 1, wherein the trench insulation material is an oxide material.

8. The method of claim 1, wherein a doping concentration of the charge linking region is lower than the doping concentration of the body region.

9. The method of claim 1, wherein the trench insulation material is of substantially uniform thickness.

10. The method of claim 1, wherein the trench insulation material is thicker at the bottom of the trenches.

11. The method of claim 1, wherein the trench insulation material is thickness is tapered higher near the trench bottom.

12. The method of claim 1, wherein the charge linking paths are formed by implanting dopants of the second conductivity type along one or more trench walls of one or more of the plurality of trenches.

13. The method of claim 1, wherein the charge linking paths are formed by:

a) forming a first portion of the surface shielded region on the voltage blocking region;

b) implanting dopants of the second conductivity type into the top surface of the first portion of the surface shielded region at one or more selected locations; and

c) forming a second portion of the surface shielded region above the first portion and the implanted dopants.

14. The method of claim 1, wherein each of the plurality of buried doped regions is connected to the source region by one of the one or more charge linking paths.

15. The method of claim 14, wherein the charge linking paths are formed by implanting dopants of the second conductivity type along one or more of the trench walls of each of the plurality of trenches.

16. The method of claim 14, wherein the charge linking paths are formed by the growth of an epitaxial layer along one or more of the trench walls of each one of the plurality of trenches.

17. The method of claim 14, wherein the charge linking paths are formed by:

a) forming the voltage blocking region and a first portion of the surface shielded region;

b) implanting dopants of the second conductivity type into the top surface of the surface shielded region at a location where each of the plurality of trenches will be formed; and

c) forming a second portion of the surface shielded region above the voltage blocking region and the implanted dopants.

18. A method of manufacturing a semiconductor device, comprising:

a) forming an epitaxial layer of the first conductivity type on a top surface of a semiconductor substrate of a first conductivity type, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped;

b) forming a plurality of buried doped regions of the second conductivity type, whereby each is positioned below one of the plurality of trenches, and wherein the buried doped regions extend to a depth substantially the same as the bottom surface of the surface shielded region;

c) forming one or more charge linking paths of the second conductivity type along one or more trench walls of the plurality of trenches;

d) lining the trenches are lined with a trench insulation material;

e) filling remaining portions of the trenches with an electrically conductive trench filling material;

f) forming body regions of a second conductivity type that is opposite of the first conductivity type near the top surface of the surface shielded region, wherein the one or more charge linking paths are configured to electrically connect the buried doped regions to the body regions;

f) forming source regions of the first conductivity type near the top surface of the surface shielded region, wherein the trench filling material is configured to be in electrical contact with the source regions;

g) forming a plurality of gates on the top surface of the surface shielded region.