Integrated decoupling capacitor employing conductive through-substrate vias

• US 8,785,289 B2
• Filed: 08/26/2013
• Issued: 07/22/2014
• Est. Priority Date: 11/09/2009
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Tae Hong, McAllister, Michael F., Shapiro, Michael J., Sprogis, Edmund J.
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US13/975,519
• Publication Number:
  US 20130344675A1
• Time in Patent Office: 330 Days
• Field of Search: 257/301, 257/532, 257/E21.597, 438/387, 438/667
• US Class Current: 438/386
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV'"'"'s can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.

Claims

1. A method of forming a semiconductor structure comprising:

forming a capacitor and an laterally-insulated conductive through-substrate connection structure in a semiconductor substrate,

wherein said forming said laterally-insulated conductive through-substrate connection structure and said capacitor comprises;

forming a dielectric tubular structure around a first through-substrate cavity formed in said semiconductor substrate;

filling said first through-substrate cavity with a disposable material;

forming an outer electrode by doping a portion of said semiconductor substrate around a second through-substrate cavity;

forming a node dielectric on a surface of said second through-substrate cavity;

removing said disposable material from said first through-substrate cavity within said dielectric tubular structure;

filling said first through-substrate cavity with said dielectric tubular structure with a conductive material; and

forming an inner electrode by filling said second through-substrate cavity with said conductive material.

2. The method of claim 1, wherein said inner electrode constitutes a first conductive through-substrate via (TSV) structure, a second conductive TSV structure is formed in said cavity filled by said conductive material, and said first conductive TSV structure and said second conductive TSV structure are formed concurrently.

3. The method of claim 2, wherein at least one of the first TSV, and the second TSV is composed of a material selected from the group consisting of doped polysilicon, doped silicon-containing alloy, Cu, W, Ta, Ti, WN, TaN, TiN, or a combination thereof.

4. The method of claim 2, wherein at least one of the first TSV and the second TSV by electroplating, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof.

5. The method of claim 1, wherein the disposable material is polysilicon or amorphous silicon.

6. The method of claim 1, further comprising forming said node dielectric directly on sidewalls of said doped tubular portion while said disposable material is present in said semiconductor substrate.

7. The method of claim 6, wherein the node dielectric has a thickness ranging from 3 nm to 30 nm.

8. The method of claim 1, further comprising:

filling said second through-substrate cavity with a second disposable material after forming said outer electrode;

forming a hard mask layer on one side of said semiconductor substrate; and

removing said disposable material and said second disposable material employing said hard mask layer as an etch mask.

9. A method of forming a semiconductor structure comprising:

providing a semiconductor chip including;

providing a semiconductor substrate;

forming at least one capacitor embedded in said semiconductor substrate, said at least one capacitor including an inner electrode comprising a conductive through-substrate via (TSV) structure; and

forming at least one laterally-insulated conductive through-substrate connection structure, wherein said forming at least one laterally-insulated conductive through-substrate connection structure comprises;

forming a dielectric tubular structure around a first through-substrate cavity formed in said semiconductor substrate,

filling said first through-substrate cavity with a disposable material,

removing said disposable material from said first through-substrate cavity within said dielectric tubular structure before forming said inner electrode of said at least one capacitor, and

filling said cavity within said dielectric tubular structure with a conductive material; and

electrically connecting said semiconductor chip to a mounting structure employing an array of solder balls.

10. The method of claim 9, wherein the conductive TSV is composed of a material selected from the group consisting of doped polysilicon, doped silicon-containing alloy, Cu, W, Ta, Ti, WN, TaN, TiN, or a combination thereof.

11. The method of claim 9, wherein the mounting structure includes an interposer structure.

12. The method of claim 9, wherein the semiconductor chip further comprises field effect transistors, thyristors, bipolar transistors, diodes and combinations thereof.

13. The method of claim 9, wherein the capacitors are decoupling capacitors.

14. The method of claim 13, wherein the decoupling capacitors have a capacitance ranging from 1 pF to 10 nF.

15. The method of claim 11, wherein the interposer includes a dielectric layer and a plurality of metal lines.

16. The method of claim 9, wherein first solder balls among said array are electrically connected to said inner electrodes and first conductive structures on said mounting structure, and second solder balls among said array are electrically connected to conductive TSV structures within said at least one laterally-insulated conductive through-substrate connection structure and second conductive structures on said mounting structure.

17. The method of claim 9, wherein said mounting structure is selected from a packaging substrate, an interposer structure, and another semiconductor chip.

18. The method of claim 9, wherein each of said at least one capacitor includes a node dielectric laterally contacting and laterally enclosing said inner electrode and an outer electrode laterally contacting and laterally enclosing a portion of said node dielectric, and each of said at least one laterally-insulated conductive through-substrate connection structure includes a conductive TSV structure and a dielectric tubular structure.