Conductive layers for hafnium silicon oxynitride

• US 8,785,312 B2
• Filed: 11/28/2011
• Issued: 07/22/2014
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US13/305,338
• Publication Number:
  US 20120068272A1
• Time in Patent Office: 967 Days
• Field of Search: 438/591, 438/785, 438/786, 438/791, 257/E21.19, 257/369, 257/296, 257/310
• US Class Current: 438/591
• CPC Class Codes: C23C 16/30 Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: C23C 16/45531 specially adapted for making ternary or higher compositions
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 21/318 composed of nitrides
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.

Claims

1. A method comprising:

forming a dielectric including hafnium silicon oxynitride, the hafnium silicon oxynitride being Hf_xSi_yO_zN_r with x>

0, y>

0, z>

0, and r>

0;

forming the hafnium silicon oxynitride doped with one or more elements other than hafnium or silicon, such that the hafnium silicon oxynitride is maintained as a hafnium silicon oxynitride structure, by using a monolayer or partial monolayer sequencing process and by substituting a sequence of the one or more elements for a hafnium sequence of a plurality of hafnium sequences or substituting a sequence of the one or more elements for a silicon sequence of a plurality of silicon sequences in the monolayer or partial monolayer sequencing process such that the one or more elements are included in a completed structure of the hafnium silicon oxynitride; and

forming a conductive material coupled to the dielectric.

2. The method of claim 1, wherein forming the conductive includes forming titanium nitride coupled to the hafnium silicon oxynitride.

3. The method of claim 1, wherein forming the conductive includes forming tantalum coupled to the hafnium silicon oxynitride.

4. The method of claim 1, wherein forming the dielectric includes forming the dielectric as a nanolaminate.

5. The method of claim 1, wherein forming the conductive material includes forming the conductive material using the monolayer or partial monolayer sequencing process.

6. The method of claim 5, wherein using the monolayer or partial monolayer sequencing process includes using atomic layer deposition.

7. The method of claim 1, wherein forming hafnium silicon oxynitride includes:

forming alternating layers of hafnium oxide and silicon nitride; and

annealing the alternating layers of hafnium oxide and silicon nitride to form hafnium silicon oxynitride.

8. The method of claim 7, wherein annealing includes annealing in a nitrogen ambient.

9. The method of claim 1, wherein the method includes:

forming tantalum as the conductive material coupled to the hafnium silicon oxynitride such that the tantalum is formed as a gate with the hafnium silicon oxynitride as a gate insulator in a PMOS transistor of a CMOS structure; and

forming a titanium nitride as a gate on another region of hafnium silicon oxynitride in a NMOS transistor of the CMOS structure.

10. The method of claim 1, wherein forming the dielectric includes forming the dielectric essentially as the hafnium silicon oxynitride.

11. The method of claim 1, wherein forming the dielectric includes forming a stack of dielectrics.

12. The method of claim 11, wherein forming the stack of dielectrics includes forming an insulating metal oxide.

16. The method of claim 1, wherein hafnium silicon oxynitride is formed in each cycle of the monolayer or partial monolayer sequencing process.

17. The method of claim 1, wherein a number of hafnium sequence and a number of silicon sequences are conducted in each cycle of the monolayer or partial monolayer sequencing process such that the hafnium silicon oxynitride is formed being a hafnium-rich hafnium silicon oxynitride.

13. A method comprising:

forming a memory having a dielectric including hafnium silicon oxynitride, the hafnium silicon oxynitride being Hf_xSi_yO_zN_r with x>

0, y>

0, z>

0, and r>

0;

forming the hafnium silicon oxynitride doped with one or more elements other than hafnium or silicon, such that the hafnium silicon oxynitride is maintained as a hafnium silicon oxynitride structure, by using a monolayer or partial monolayer sequencing process and substituting a sequence of the one or more elements for a hafnium sequence of a plurality of hafnium sequences or substituting a sequence of the one or more elements for a silicon sequence of a plurality of silicon sequences in the monolayer or partial monolayer sequencing process such that the one or more elements are included in a completed structure of the hafnium silicon oxynitride; and

forming one or more of a titanium nitride or tantalum coupled to the dielectric.

14. The method of claim 13, wherein the method includes forming the dielectric as a nanolaminate containing silicon oxide as a charge storage region of the nanolaminate.

15. The method of claim 13, wherein the method includes forming titanium nitride as a gate with the hafnium silicon oxynitride as a gate insulator in a NMOS transistor and forming tantalum as a gate with a region of hafnium silicon oxynitride as a gate insulator in a PMOS transistor such that the NMOS transistor and the PMOS transistor have substantially symmetrical threshold voltages.