Power semiconductor device and a method for forming a semiconductor device
First Claim
1. A power semiconductor device comprising:
- a semiconductor body comprising;
an active area and a peripheral area which both define a horizontal main surface of the semiconductor body, wherein the peripheral area forms an edge of the semiconductor body;
an n-type semiconductor layer which is beneath the main surface in the active area and extends to the main surface in the peripheral area;
a pn junction which is arranged between the n-type semiconductor layer and the main surface in the active area; and
at least one trench which extends in the peripheral area from the main surface into the n-type semiconductor layer and comprises a dielectric layer comprising fixed negative charges and being, in a vertical direction which is substantially perpendicular to the main surface, arranged both below and above the pn junction.
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Abstract
A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.
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Citations
15 Claims
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1. A power semiconductor device comprising:
a semiconductor body comprising; an active area and a peripheral area which both define a horizontal main surface of the semiconductor body, wherein the peripheral area forms an edge of the semiconductor body; an n-type semiconductor layer which is beneath the main surface in the active area and extends to the main surface in the peripheral area; a pn junction which is arranged between the n-type semiconductor layer and the main surface in the active area; and at least one trench which extends in the peripheral area from the main surface into the n-type semiconductor layer and comprises a dielectric layer comprising fixed negative charges and being, in a vertical direction which is substantially perpendicular to the main surface, arranged both below and above the pn junction. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A vertical semiconductor transistor, comprising:
a semiconductor body comprising; a first n-type semiconductor region; a second semiconductor region which forms a pn junction with the first semiconductor region; a third semiconductor region; and a dielectric layer which comprises fixed negative charges in at least one portion, adjoins the second semiconductor region and is arranged between the first semiconductor region and the third semiconductor region; and an insulated gate electrode adjacent to the first semiconductor region and the second semiconductor region and separated from the dielectric layer by the second semiconductor region. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
Specification