Power semiconductor device and a method for forming a semiconductor device

• US 8,786,012 B2
• Filed: 07/06/2012
• Issued: 07/22/2014
• Est. Priority Date: 07/26/2010
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Mauder, Anton, Hirler, Franz, Lehnert, Wolfgang, Berger, Rudolf, Pruegl, Klemens, Schulze, Hans-Joachim, Strack, Helmut
• Primary Examiner(s): Ullah, Elias M
• Application Number:
  US13/542,737
• Publication Number:
  US 20120286355A1
• Time in Patent Office: 746 Days
• Field of Search: 257/330, 257/622, 257/E29.002, 257/E21.214, 257/E29.262, 438/702
• US Class Current: 257/330
• CPC Class Codes: H01L 21/02109 characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
• CPC Class Codes: H01L 21/02145 the material containing aluminium, e.g. AlSiOx
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/8611 : Planar PN junction diodes

Abstract

A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

Claims

1. A power semiconductor device comprising:

a semiconductor body comprising;

an active area and a peripheral area which both define a horizontal main surface of the semiconductor body, wherein the peripheral area forms an edge of the semiconductor body;

an n-type semiconductor layer which is beneath the main surface in the active area and extends to the main surface in the peripheral area;

a pn junction which is arranged between the n-type semiconductor layer and the main surface in the active area; and

at least one trench which extends in the peripheral area from the main surface into the n-type semiconductor layer and comprises a dielectric layer comprising fixed negative charges and being, in a vertical direction which is substantially perpendicular to the main surface, arranged both below and above the pn junction.

2. The power semiconductor device of claim 1, wherein a charge carrier density per area of the fixed negative charges of the dielectric layer decreases step-wise or continuously with increasing distance from the main surface.

3. The power semiconductor device of claim 1, wherein the dielectric layer comprises an aluminum-doped silicon oxide and/or an aluminum-doped oxynitride.

4. The power semiconductor device of claim 1, wherein the at least one trench comprises a cavity.

5. The power semiconductor device claim 1, wherein the pn junction adjoins the dielectric layer.

6. The power semiconductor device of claim 1, wherein the dielectric layer has a negative net charge, the power semiconductor device further comprising a further trench which extends in the peripheral area from the main surface into the n-type semiconductor layer and comprises a further dielectric layer having a positive net charge, the further dielectric layer, in the vertical direction, being arranged both below and above the pn junction.

7. The power semiconductor device of claim 6, wherein at least one portion of the at least one trench and/or a portion of the further trench forms an acute angle with the active area.

8. A vertical semiconductor transistor, comprising:

a semiconductor body comprising;

a first n-type semiconductor region;

a second semiconductor region which forms a pn junction with the first semiconductor region;

a third semiconductor region; and

a dielectric layer which comprises fixed negative charges in at least one portion, adjoins the second semiconductor region and is arranged between the first semiconductor region and the third semiconductor region; and

an insulated gate electrode adjacent to the first semiconductor region and the second semiconductor region and separated from the dielectric layer by the second semiconductor region.

9. The vertical semiconductor transistor of claim 8, wherein the dielectric layer extends from a main surface of the semiconductor body into the semiconductor body, and wherein a charge carrier density per area of the fixed negative charges of the dielectric layer decreases step-wise or continuously with increasing distance from the main surface.

10. The vertical semiconductor transistor of claim 8, wherein the dielectric layer comprises an aluminum-doped silicon oxide or an aluminum-doped oxynitride.

11. The vertical semiconductor transistor of claim 8, wherein the vertical semiconductor transistor is a TEDFET, and wherein the dielectric layer forms an accumulation oxide.

12. The vertical semiconductor transistor of claim 8, wherein the dielectric layer is arranged in a vertical trench which extends from a main surface of the semiconductor body to a back surface of the semiconductor body arranged opposite the main surface.

13. The vertical semiconductor transistor of claim 8, wherein a charge carrier density per area of the fixed negative charges of the dielectric layer in a horizontal plane has a highest value approximately in a center region between the third semiconductor region and the first semiconductor region.

14. The vertical semiconductor transistor of claim 8, wherein the dielectric layer has a negative net charge in the at least one portion, and wherein the dielectric layer has a positive net charge in at least one further portion.

15. The vertical semiconductor transistor of claim 8, further comprising a further dielectric layer having a positive net charge, the further dielectric layer extending from a main surface of the semiconductor body into the semiconductor body.