Trench transistor
First Claim
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1. A semiconductor device comprising:
- a substrate defined with a device region;
a buried heavily doped drain region in the substrate in the device region;
a gate in a trench in the device region, wherein a channel of the device is disposed on a sidewall of the trench, the buried heavily doped drain region is disposed below the gate and is vertically and laterally displaced away from the channel of the device, wherein a distance from the buried heavily doped drain region to the channel is a drift length LD of the device;
a drain connector disposed in the trench and is connected to the buried heavily doped drain region, wherein the drain connector is isolated from the gate; and
a surface heavily doped region adjacent to the gate.
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Abstract
A method of forming a device is disclosed. A substrate defined with a device region is provided. A buried doped region is formed in the substrate in the device region. A gate is formed in a trench in the substrate in the device region. A channel of the device is disposed on a sidewall of the trench. The buried doped region is disposed below the gate. A distance from the buried doped region to the channel is a drift length LD of the device. A surface doped region is formed adjacent to the gate.
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Citations
18 Claims
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1. A semiconductor device comprising:
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a substrate defined with a device region; a buried heavily doped drain region in the substrate in the device region; a gate in a trench in the device region, wherein a channel of the device is disposed on a sidewall of the trench, the buried heavily doped drain region is disposed below the gate and is vertically and laterally displaced away from the channel of the device, wherein a distance from the buried heavily doped drain region to the channel is a drift length LD of the device; a drain connector disposed in the trench and is connected to the buried heavily doped drain region, wherein the drain connector is isolated from the gate; and a surface heavily doped region adjacent to the gate. - View Dependent Claims (2, 3, 4, 5, 6)
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7. The semiconductor device of 6 wherein:
the trench is disposed in the first and second device doped wells and the trench comprises first and second portions. - View Dependent Claims (8, 10)
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9. A semiconductor device comprising:
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a substrate defined with a device region; a buried heavily doped drain region in the substrate in the device region; a gate in a trench in the device region, wherein a channel of the device is disposed on a sidewall of the trench, the buried heavily doped drain region is disposed below the gate and is vertically and laterally displaced away from the channel of the device, wherein a distance from the buried heavily doped drain region to the channel is a drift length LD of the device; a drain connector disposed in the trench and is connected to the buried heavily doped drain region, wherein the drain connector is isolated from the gate; a gate dielectric layer which lines sidewalls and bottom of a first portion of the trench without lining sidewalls of the drain connector; and a surface heavily doped region adjacent to the gate.
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11. A semiconductor device comprising:
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a substrate defined with a device region; first and second device doped wells in the device region, wherein the first device doped well has a depth greater than the second device doped well; a buried heavily doped region which is disposed within the first device doped well; a gate in a trench in the device region, the trench has a depth greater than an interface of the first and second device doped wells, wherein a channel of the device is disposed on a sidewall of the trench, the buried heavily doped region is disposed below the gate and is vertically and laterally displaced away from the gate and channel of the device, wherein a distance from the buried heavily doped region to the channel is a drift length LD of the device; a drain connector disposed in the trench, wherein the drain connector is disposed adjacent to the gate and extends from a top surface of the substrate to the buried heavily doped region; a gate dielectric layer which lines sidewalls and bottom of the trench without lining sidewalls of the drain connector; and a surface heavily doped region adjacent to the gate. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification