Power semiconductor devices having termination structures

• US 8,786,045 B2
• Filed: 09/09/2010
• Issued: 07/22/2014
• Est. Priority Date: 05/20/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok, Lee, Jaegil, Jung, Jinyoung, Jang, Hocheol
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): BODNAR, JOHN A
• Application Number:
  US12/878,429
• Publication Number:
  US 20110001189A1
• Time in Patent Office: 1,412 Days
• Field of Search: 257490-495, 257/E29.009, 257/488
• US Class Current: 257/490
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

In one general aspect, a termination structure can include a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type where the plurality of pillars define a plurality of concentric rings surrounding an active area of a semiconductor device. The termination structure can include a conductive field plate where the plurality of pillars includes a first pillar coupled to the conductive field plate. The termination structure can include a dielectric layer where the plurality of pillars include a second pillar insulated by the dielectric layer from a portion of the conductive field plate disposed directly above the second pillar included in the plurality of pillars.

Claims

1. A termination structure, comprising:

a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type, the plurality of pillars defining a plurality of concentric rings surrounding an active area of a semiconductor device;

a conductive field plate, the plurality of pillars including a first pillar coupled to the conductive field plate; and

a dielectric layer, the plurality of pillars including a second pillar insulated by the dielectric layer from a portion of the conductive field plate disposed directly above the second pillar included in the plurality of pillars.

2. The termination structure of claim 1, wherein the conductive field plate is a first conductive field plate coupled to the first pillar, the conductive field plate is made of a conductive material that covers and is dielectrically isolated from the second pillar by the dielectric layer,

the termination structure further comprising:

a second conductive field plate coupled to a third pillar from the plurality of pillars.

3. The termination structure of claim 1, wherein the conductive field plate is coupled to ground.

4. The termination structure of claim 1, wherein a center-to-center spacing between each pair of adjacent pillars from the plurality of pillars varies with a distance from an edge of the active area.

5. The termination structure of claim 1, wherein a center-to-center spacing between each pair of adjacent pillars from the plurality of pillars increases with a distance from an edge of the active area.

6. The termination structure of claim 1, wherein a width of each pillar from the plurality of pillars varies with a distance from an edge of the active area.

7. The termination structure of claim 1, wherein a width of each pillar from the plurality of pillars decreases with a distance from an edge of the active area.

8. The termination structure of claim 1, wherein a top surface of the second pillar from the plurality of pillars is covered by the dielectric layer.

9. The termination structure of claim 1, wherein the conductive field plate coupled to the first pillar extends over and is insulated from the second pillar from the plurality of pillars by the dielectric layer.

10. The termination structure of claim 1, wherein the first pillar has a length at least five times greater than a width of the first pillar.

11. The termination structure of claim 1, wherein the plurality of pillars are p-type pillars, the p-type pillars decrease in charge with distance from the active area such that a net n-type balance charge is formed in at least a portion of the termination region.

12. The termination structure of claim 1, wherein at least a portion of the termination region of the second conductivity type is an epitaxial layer, the first pillar extends to a depth more than half of a thickness of the epitaxial layer.

13. An apparatus, comprising:

a first conductive field plate;

a second conductive field plate;

a dielectric layer; and

a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type, the plurality of pillars defining a plurality of concentric rings disposed outside of an active area of a semiconductor device,

the plurality of pillars including a first pillar coupled to the first conductive field plate and including a second pillar coupled to the second conductive field plate, the plurality of pillars including a third pillar isolated from the second conductive field plate by the dielectric layer, the dielectric layer being contiguous between the first pillar included in the plurality of pillars and the second pillar included in the plurality of pillars, the plurality of pillars being p-type pillars, the p-type pillars decreasing in charge with distance from the active area such that a net n-type balance charge is formed in at least a portion of the termination region.

14. The apparatus of claim 13, wherein at least a portion of the termination region of the second conductivity type is an epitaxial layer, the first pillar and the third pillar each extend to a depth more than half of a thickness of the epitaxial layer.

17. The apparatus of claim 13, further comprising:

a first mesa region disposed between the first pillar included in the plurality of pillars and the second pillar included in the plurality of pillars; and

a second mesa region disposed between the second pillar included in the plurality of pillars and the third pillar included in the plurality of pillars, the first mesa region having a width greater than a width of the second mesa region.

18. The apparatus of claim 13, wherein the second pillar is a last pillar from the plurality of pillars.

15. A termination structure, comprising:

a conductive field plate;

a plurality of pillars of a first conductivity type inside a termination region of a second conductivity type opposite the first conductivity type, the plurality of pillars defining a plurality of concentric rings surrounding an active area of a semiconductor device;

a dielectric layer, the plurality of pillars including a first pillar coupled to the conductive field plate and including a second pillar disposed between first pillar included in the plurality of pillars and a third pillar included in the plurality of pillars, the second pillar included in the plurality of pillars being isolated from the conductive field plate by the dielectric layer, the dielectric layer being contiguous between the first pillar included in the plurality of pillars and the third pillar included in the plurality of pillars;

a first mesa region disposed between the first pillar included in the plurality of pillars and the second pillar included in the plurality of pillars; and

a second mesa region disposed between the second pillar included in the plurality of pillars and the third pillar included in the plurality of pillars, the first mesa region having a width greater than a width of the second mesa region.

16. The termination structure of claim 15, wherein the plurality of pillars are p-type pillars, the p-type pillars decrease in charge with distance from the active area such that a net n-type balance charge is formed in at least a portion of the termination region.

19. The termination structure of claim 15, wherein the plurality of pillars define a charge balance with the active area such that a breakdown voltage of the termination region is substantially equal to a breakdown voltage of the active area.

20. The termination structure of claim 15, wherein a distance between a pair of pillars from the plurality of pillars is approximately twice a distance between the plurality of pillars and an end of an active trench in the active area.