Semiconductor device with chip having low-k-layers

• US 8,786,105 B1
• Filed: 01/11/2013
• Issued: 07/22/2014
• Est. Priority Date: 01/11/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Mobile Communications GmbH (Intel Corporation)
• Inventors: Meyer, Thorsten, Albers, Sven, Geissler, Christian, Wolter, Andreas, Brunnbauer, Markus, O'Sullivan, David, Zudock, Frank, Proschwitz, Jan
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US13/739,045
• Publication Number:
  US 20140197530A1
• Time in Patent Office: 557 Days
• Field of Search: 257/621, 257/737, 257/738, 257/778, 257/E23.021, 257/E23.069, 257/E21.503, 438/108, 438612-617, 438/112
• US Class Current: 257/778
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

Claims

1. A semiconductor device comprising:

at least one semiconductor chip, the chip comprising;

an active area on a top side of the at least one semiconductor chip, the active area being formed at least in part of a low-k material defining a low-k sub-area of the active area;

an embedding material embedding the at least one semiconductor chip, wherein at least part of the embedding material forms a coplanar area with the active area;

at least one contact area disposed within the low-k sub-area; and

at least one interconnect, located outside the low-k sub-area, the interconnect electrically connected to the at least one contact area.

2. The device of claim 1, further comprising:

a redistribution layer disposed on the coplanar area, wherein the redistribution layer is electrically connected to the at least one contact area.

3. The device of claim 2, wherein the at least one interconnect is electrically connected to the at least one contact area via the redistribution layer.

4. The device of claim 3, further comprising:

a dielectric layer disposed on the coplanar area.

5. The device of claim 3, further comprising:

a protection layer disposed over the low-k sub-area.

6. The device of claim 5, wherein the protection layer is composed of one or more materials selected from the group consisting of:

silicone, polyurethane, epoxy, polyimide.

7. The device of claim 5, wherein the protection layer comprises silicone particles with one of the following fillers:

air gaps, air foams, bubbles.

8. The device of claim 3, further comprising:

a lid disposed over the active area.

9. The device of claim 8, wherein the lid is one of a polymer lid, a metal lid and a ceramic lid.

10. The device of claim 8, wherein the lid is glued, soldered, clamped, or bonded to the active area.

11. The device of claim 1, wherein the at least one interconnect is located on a back side of the at least one semiconductor chip.

12. The device of claim 11, wherein the at least one interconnect is electrically connected to the at least one contact area by at least one through-silicon-via.

13. The device of claim 12, wherein the low-k sub-area is mechanically decoupled from the back side of the at least one chip by at least one layer of silicon.

14. The device of claim 1, further comprising:

a substrate electrically connected to the at least one interconnect.

15. The device of claim 1, wherein the at least one interconnect is a flip-chip bump or a copper pillar.

16. A semiconductor device comprising:

at least one semiconductor chip, the chip comprising;

an active area on a top side of the at least one semiconductor chip, the active area being formed at least in part of a low-k material defining a low-k sub-area of the active area;

an embedding material embedding the at least one semiconductor chip, wherein at least part of the embedding material forms a coplanar area with the active area;

at least one contact area disposed within the low-k sub-area;

a redistribution layer disposed on the coplanar area, wherein the redistribution layer is electrically connected to the at least one contact area;

at least one interconnect, located outside the low-k subarea, the interconnect electrically connected to the at least one contact area via the redistribution layer.

17. The device of claim 16, further comprising:

a dielectric layer disposed on the coplanar area.

18. The device of claim 16, further comprising:

a protection layer applied over the low-k sub-area.

19. The device of claim 18, wherein the protection layer is composed of one or more materials selected from the group consisting of:

silicone, polyurethane, epoxy, polyimide.

20. The device of claim 18, wherein the protection layer contains silicone particles with one of the following fillers:

air gaps, air foams, bubbles.

21. The device of claim 16, further comprising:

a lid disposed over the active area.

22. The device of claim 21, wherein the lid is one of a polymer lid, a metal lid and a ceramic lid.

23. The device of claim 21, wherein the lid is glued, soldered, clamped, or bonded to the active area.

24. The device of claim 16, further comprising:

a substrate electrically connected to the at least one interconnect.

25. The device of claim 16, wherein the at least one interconnect is a flip-chip bump or a copper pillar.

26. A method of producing a semiconductor device, comprising:

embedding a semiconductor chip, including a top side with an active area formed at least part of low-k material defining a low-k sub-area, into an embedding material;

forming a planar surface on the embedding material, the active area coplanar with the embedding material;

disposing at least one contact area within the low-k sub-area;

disposing a redistribution layer on the coplanar area, the redistribution layer electrically connected to the at least one contact area;

forming at least one interconnect outside the low-k sub-area, the at least one interconnect electrically connected to the at least one contact area within the low-k sub-area via the redistribution layer.

27. The method of claim 26, further comprising:

depositing a dielectric layer on the coplanar area.

28. The method of claim 26, further comprising:

depositing a protection layer over the low-k sub-area.

29. The method of claim 26, further comprising:

disposing a lid over the low-k sub-area.

30. The method of claim 26, further comprising:

connecting a substrate electrically with the at least one interconnect.