System for reducing noise in a chemical sensor array

• US 8,786,331 B2
• Filed: 03/13/2013
• Issued: 07/22/2014
• Est. Priority Date: 05/29/2012
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Jordan, Jeremy, Rearick, Todd
• Primary Examiner(s): Cole, Brandon S
• Application Number:
  US13/801,709
• Publication Number:
  US 20130321044A1
• Time in Patent Office: 496 Days
• Field of Search: 327/165, 327/166, 327291-299, 327365-508, 327/178, 326 93- 98, 716/6
• US Class Current: 327/141
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents

Abstract

A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.

Claims

1. A system comprising:

a first analog-to-digital converter to receive an output signal from a sensor array;

a first switcher to power the sensor array and the first analog-to-digital converter; and

a clock generator to generate a plurality of clock signals that are synchronous with a primary clock signal,

the clock generator provides a first clock signal of the plurality to the first analog-to-digital converter and provides a second clock signal of the plurality to the first switcher, the first clock signal is asynchronous with the second clock signal.

2. The system of claim 1, wherein a sensor in the sensor array is at least one of a chemically-sensitive field effect transistor (chemFET) and an ion-sensitive field effect transistor (ISFET).

3. The system of claim 2, wherein the chemFET/ISFET detects a chemical reaction occurring proximate to the chemFET/ISFET.

4. The system of claim 1, wherein the sensor array includes an output circuit to receive output signals from the sensor array.

5. The system of claim 4, wherein the sensor array includes an output circuit to provide the output signals to the first analog-to-digital converter.

6. The system of claim 1, wherein the system further includes a second switcher responsive to a third clock signal that is asynchronous with the first clock signal such that a power consumption on a power supply from the second switcher is staggered.

7. The system of claim 1, wherein the system further includes a second switcher responsive to a third clock signal having a rising edge that is concurrent with a falling edge of the first clock signal.

8. The system of claim 1, wherein the first and second switchers are disposed on a same substrate.

9. The system of claim 1, wherein the analog-to-digital converter and the sensor array are disposed on a same substrate.

10. The system of claim 1, wherein the analog-to-digital converter is disposed on a first substrate and the sensor array is disposed on a second substrate.

11. The system of claim 1, wherein a power supply provides power to a first switcher on a first substrate and provides power to a second switcher on a second substrate.

12. A system comprising:

a first analog-to-digital converter to receive an output signal from a sensor array;

a first switcher to power the sensor array and the first analog-to-digital converter; and

a clock generator to generate a plurality of clock signals that are synchronous with a primary clock signal,

the clock generator provides a first clock signal of the plurality to the first analog-to-digital converter and provides a second clock signal of the plurality to the first switcher, the first clock signal is asynchronous with the second clock signal, wherein

a power supply provides power to a first switcher on a first substrate and the first switcher provides power to a second switcher on a second substrate.