Display device and driving method thereof

• US 8,786,588 B2
• Filed: 02/18/2011
• Issued: 07/22/2014
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Primary Examiner(s): Mengistu, Amare
• Assistant Examiner(s): ZUBAJLO, JENNIFER L
• Application Number:
  US13/030,184
• Publication Number:
  US 20110210957A1
• Time in Patent Office: 1,250 Days
• Field of Search: 345/87, 345/99, 345/212, 345/213, 345/211
• US Class Current: 345/211
• CPC Class Codes: G06F 1/3218 of display devices
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G09G 2310/0202 Addressing of scan or signal lines
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/103 Detection of image changes, e.g. determination of an index representative of the image change
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a still image display mode, a driving signal and power supply voltage are supplied to a first driver circuit and a driving signal and power supply voltage are supplied to a second driver circuit, and an image signal is output to n pixels. After that, at least the supply of the driving signal and the power supply voltage to the second driver circuit is stopped and an image of the pixel portion based on the image signal is held as a still image. A series of these operations is performed N (N is a natural number) times. In the case where N is 2 or more, stopping the supply of the driving signal and the power supply voltage to the second driver circuit in a K-th (K is a natural number, 2≦K≦N) period is set longer than that in a (K−1)-th period.

Claims

1. A method for driving a display device comprising a driver circuit portion and a pixel portion comprising n (n is a natural number) pixels, the driver circuit portion comprising a first driver circuit and a second driver circuit, wherein each of the n pixels comprises a transistor, and wherein a channel formation region of the transistor comprises an oxide semiconductor layer, comprising the step of:

performing operation N (N is a natural number) times in a still image display mode for displaying a still image in the pixel portion, the operation comprising;

supplying a first driving signal and a first power supply voltage to the first driver circuit;

supplying a second driving signal and a second power supply voltage to the second driver circuit;

supplying a scan signal to the n pixels from the first driver circuit;

supplying an image signal to the n pixels from the second driver circuit;

stopping supply of the second driving signal and the second power supply voltage to the second driver circuit; and

holding an image of the pixel portion based on the image signal as the still image,

wherein in the case where N is greater than or equal to 2, a K-th (K is a natural number greater than or equal to 2 and less than or equal to N) period of stopping supply of the second driving signal and the second power supply voltage to the second driver circuit is set longer than a (K−

1)-th period of stopping supply of the second driving signal and the second power supply voltage to the second driver circuit.

2. The method for driving a display device, according to claim 1, wherein the operation further comprises stopping supply of the first driving signal and the first power supply voltage to the first driver circuit after supplying the image signal to the n pixels.

3. The method for driving a display device, according to claim 1, wherein in the case where an operation signal is input to the display device in a (K+1)-th period of holding the image, supply of the first driving signal, and the first power supply voltage to the first driver circuit is started and supply of the second driving signal, and the second power supply voltage to the second driver circuit is started, and the image signal is supplied to the n pixels.

4. The method for driving a display device, according to claim 1,

wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

5. The method for driving a display device, according to claim 1,

wherein each of the n pixels comprises:

the transistor comprising a gate, a source, and a drain; and

a liquid crystal element,

wherein the gate is electrically connected to the first driver circuit,

wherein one of the source and the drain is electrically connected to the second driver circuit, and

wherein the other of the source and the drain is electrically connected to the liquid crystal element.

6. The method for driving a display device, according to claim 1, wherein the pixel portion has a moving image display mode for displaying a moving image by the n pixels and the still image display mode for displaying the still image by the n pixels.

7. The method for driving a display device, according to claim 1,

wherein the first driving signal includes a first start signal and a first clock signal, and

wherein the second driving signal includes a second start signal and a second clock signal.

8. The method for driving a display device, according to claim 1,

wherein off-state current per micrometer of a channel width of the transistor is 100 aA/μ

m.

9. The method for driving a display device, according to claim 1,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

10. A method for driving a display device comprising a driver circuit portion and a pixel portion comprising n (n is a natural number) pixels, the driver circuit portion comprising a first driver circuit and a second driver circuit, wherein each of the n pixels comprises a transistor, and wherein a channel formation region of the transistor comprises an oxide semiconductor layer, comprising the step of:

performing operation N (N is a natural number) times in a still image display mode for displaying a still image in the pixel portion, the operation comprising;

supplying a first driving signal and a first power supply voltage to the first driver circuit;

supplying a second driving signal and a second power supply voltage to the second driver circuit;

supplying a scan signal to the n pixels from the first driver circuit;

supplying an image signal to the n pixels from the second driver circuit;

stopping supply of the second driving signal and the second power supply voltage to the second driver circuit; and

holding an image of the pixel portion based on the image signal as the still image,

wherein in the case where N is greater than or equal to 2, a K-th (K is a natural number greater than or equal to 2 and less than or equal to N) period of stopping supply of the second driving signal and the second power supply voltage to the second driver circuit is set longer than a (K−

1)-th period of stopping supply of the second driving signal and the second power supply voltage to the second driver circuit, and

wherein an interval between the K-th period of supplying the image signal to the n pixels and the (K−

1)-th period of supplying the image signal is 10 seconds or longer.

11. The method for driving a display device, according to claim 10, wherein the operation further comprises stopping supply of the first driving signal and the first power supply voltage to the first driver circuit after supplying the image signal to the n pixels.

12. The method for driving a display device, according to claim 10, wherein in the case where an operation signal is input to the display device in a (K+1)-th period of holding the image, supply of the first driving signal and the first power supply voltage to the first driver circuit is started and supply of the second driving signal and the second power supply voltage to the second driver circuit is started, and the image signal is supplied to the n pixels.

13. The method for driving a display device, according to claim 10,

wherein each of the n pixels comprises:

the transistor comprising a gate, a source, and a drain; and

a liquid crystal element,

wherein the gate is electrically connected to the first driver circuit,

wherein one of the source and the drain is electrically connected to the second driver circuit, and

wherein the other of the source and the drain is electrically connected to the liquid crystal element.

14. The method for driving a display device, according to claim 10, wherein the pixel portion has a moving image display mode for displaying a moving image by the n pixels and the still image display mode for displaying the still image by the n pixels.

15. The method for driving a display device, according to claim 10,

wherein the first driving signal includes a first start signal and a first clock signal, and

wherein the second driving signal includes a second start signal and a second clock signal.

16. The method for driving a display device, according to claim 10, wherein off-state current per micrometer of a channel width of the transistor is 100 aA/μ

m.

17. The method for driving a display device, according to claim 10, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

18. The method for driving a display device, according to claim 10, wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

19. A display device comprising:

a CPU supplied with an operation signal;

a display control circuit;

a first driver circuit; and

a second driver circuit; and

n (n is a natural number) pixels,

wherein the CPU is configured to generate a first control signal and a second control signal in accordance with the operation signal, and the CPU is configured to supply the first control signal and the second control signal to the display control circuit,

wherein the display control circuit is configured to supply a first start signal, a first clock signal and power supply voltage to the first driver circuit in accordance with the first control signal, and the display control circuit is configured to supply a second start signal, a second clock signal and power supply voltage to the second driver circuit in accordance with the second control signal,

wherein the first driver circuit is configured to supply a scan signal to the n pixels,

wherein the second driver circuit is configured to supply an image signal to the n pixels, and

wherein the CPU comprises;

a counting circuit;

a latch circuit;

an arithmetic circuit; and

an output circuit,

wherein the counting circuit is configured to count the number of pulses of a reference clock signal in each period set in accordance with the operation signal and the counting circuit is configured to supply data of counted value to the latch circuit in each period as a signal,

wherein the latch circuit is configured to supply the data of counted value to the arithmetic circuit after holding the data of counted value for a certain period,

wherein the arithmetic circuit is configured to generate signals in accordance with the data of counted value and the arithmetic circuit is configured to supply the signals to the output circuit,

wherein the output circuit is configured to adjust and supply the signals to the display control circuit as the first control signal and the second control signal, and

wherein the n pixels are controlled in accordance with the scan signal and the image signal, and

wherein each of the n pixels comprises a transistor, and

wherein a channel formation region of the transistor comprises an oxide semiconductor layer.

20. The display device according to claim 19,

wherein the CPU further comprises a memory circuit configured to store data of an interval between image rewriting operations in displaying a still image, and

wherein the memory circuit is configured to supply the data of the interval to the arithmetic circuit.

21. The display device according to claim 19, wherein the CPU further comprises a reference clock signal generation circuit configured to supply the reference clock signal to the counting circuit.

22. The display device according to claim 19,

wherein the CPU further comprises an interface, and

wherein the operation signal is input to the CPU through the interface.

23. The display device, according to claim 19,

wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

24. The display device according to claim 19,

wherein each of the n pixels comprises:

the transistor comprising a gate, a source, and a drain; and

a liquid crystal element,

wherein the gate is electrically connected to the first driver circuit,

wherein one of the source and the drain is electrically connected to the second driver circuit, and

wherein the other of the source and the drain is electrically connected to the liquid crystal element.