Semiconductor device and driving method thereof

• US 8,787,084 B2
• Filed: 03/26/2012
• Issued: 07/22/2014
• Est. Priority Date: 03/30/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohmaru, Takuro
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US13/429,668
• Publication Number:
  US 20120250397A1
• Time in Patent Office: 848 Days
• Field of Search: 365/149, 365/185.05, 365/185.08, 365/189.05, 365/189.09, 365/189.2, 365/230.06
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The storage device includes a volatile first memory circuit and a nonvolatile second memory circuit which includes a transistor whose channel is formed in an oxide semiconductor layer. In the case of high-frequency driving, during a period when source voltage is applied, a data signal is input to and output from the first memory circuit, and during a part of a period when source voltage is supplied, which is before the supply of the source voltage is stopped, a data signal is input to the second memory circuit. In the case of low-frequency driving, during a period when source voltage is applied, a data signal is input to the second memory circuit, the data signal input to the second memory circuit is input to the first memory circuit, and the data signal input to the first memory circuit is output.

Claims

1. A semiconductor device comprising:

a first memory circuit;

a second memory circuit comprising a storage capacitor and a first transistor, the first transistor comprising an oxide semiconductor film including a channel formation region;

a selection circuit comprising a first input terminal, a second input terminal, and an output terminal;

a first switch; and

a second switch,

wherein the first input terminal of the selection circuit is electrically connected to the first switch and a first terminal of the first transistor,

wherein the second input terminal of the selection circuit is electrically connected to the storage capacitor and a second terminal of the first transistor, and

wherein the output terminal of the selection circuit is electrically connected to the second switch through the first memory circuit.

2. The semiconductor device according to claim 1,

wherein the first memory circuit comprises a first inverter and a second inverter,

wherein an output terminal of the first inverter is electrically connected to an input terminal of the second inverter, and

wherein an output terminal of the second inverter is electrically connected to an input terminal of the first inverter.

3. The semiconductor device according to claim 1,

wherein at least one of the selection circuit and the first memory circuit comprises a second transistor, and

wherein the second transistor has higher field effect mobility than the first transistor.

4. The semiconductor device according to claim 1,

wherein in a first case where the first switch is turned ON, the second switch is turned OFF, and

wherein in a second case where the first switch is turned OFF, the second switch is turned ON.

5. The semiconductor device according to claim 1,

wherein the first memory circuit is configured to hold a data signal only in a period when a power supply voltage is supplied.

6. The semiconductor device according to claim 1,

wherein the selection circuit is configured to perform switching from input of a signal to the first input terminal or the second input terminal to output of the signal input to the first input terminal or the second input terminal to the first memory circuit, in response to a selection signal input to the selection circuit.

7. The semiconductor device according to claim 1, further comprising:

a first node located between the first switch and the first terminal of the first transistor; and

a second node located between the storage capacitor and the second terminal of the first transistor,

wherein the first input terminal of the selection circuit is directly connected to the first node, and

wherein the second input terminal of the selection circuit is directly connected to the second node.

8. The semiconductor device according to claim 1, wherein the second memory circuit is a nonvolatile memory circuit.

9. The semiconductor device according to claim 8, wherein the first memory circuit is a volatile memory circuit.

11. The driving method according to claim 8,

wherein the first memory circuit comprises a first inverter and a second inverter,

wherein an output terminal of the first inverter is electrically connected to an input terminal of the second inverter, and

wherein an output terminal of the second inverter is electrically connected to an input terminal of the first inverter.

10. A driving method of a semiconductor device comprising a storage device, the storage device comprising:

a first memory circuit;

a second memory circuit comprising a storage capacitor and a first transistor, the first transistor comprising an oxide semiconductor film including a channel formation region;

a selection circuit comprising a first input terminal, a second input terminal, and an output terminal;

a first switch; and

a second switch, wherein the first input terminal of the selection circuit is electrically connected to the first switch and a first terminal of the first transistor, wherein the second input terminal of the selection circuit is electrically connected to the storage capacitor and a second terminal of the first transistor, and wherein the output terminal of the selection circuit is electrically connected to the second switch through the first memory circuit,

the driving method, in a high frequency operation mode, comprising the steps of;

turning the first switch ON, turning the first transistor OFF, and inputting a first data signal to the first memory circuit;

turning the first switch OFF, turning the first transistor ON, and inputting the first data signal stored in the volatile memory circuit to the storage capacitor;

stopping application of a first power supply voltage to the storage device after inputting the first data signal to the storage capacitor;

resuming application of the first power supply voltage to the storage device; and

switching the selection circuit and inputting the first data signal stored in the storage capacitor to the first memory circuit, and

the driving method, in a low frequency operation mode, comprising the steps of;

turning the first switch ON, turning the first transistor ON, and inputting a second data signal to the first memory circuit and the storage capacitor;

turning the first transistor OFF and stopping application of a second power supply voltage to the storage device after inputting the second data signal to the storage capacitor;

resuming application of the second power supply voltage to the storage device; and

switching the selection circuit and inputting the second data signal stored in the storage capacitor to the first memory circuit.

12. The driving method according to claim 10,

wherein at least one of the selection circuit and the first memory circuit comprises a second transistor, and

wherein the second transistor has higher field effect mobility than the first transistor.

13. The driving method according to claim 10,

wherein in a first case where the first switch is turned ON, the second switch is turned OFF, and

wherein in a second case where the first switch is turned OFF, the second switch is turned ON.

14. The driving method according to claim 10,

wherein the first memory circuit is configured to hold a data signal only in a period when a power supply voltage is supplied.

15. The driving method according to claim 10,

wherein the storage device further comprises:

a first node located between the first switch and the first terminal of the first transistor; and

a second node located between the storage capacitor and the second terminal of the first transistor,

wherein the first input terminal of the selection circuit is electrically connected to the first node, and

wherein the second input terminal of the selection circuit is electrically connected to the second node.

16. The driving method according to claim 10, wherein the second memory circuit is a nonvolatile memory circuit.

17. The driving method according to claim 16, wherein the first memory circuit is a volatile memory circuit.

18. A driving method of a semiconductor device comprising a storage device, the storage device comprising:

a first memory circuit;

a second memory circuit comprising a storage capacitor and a first transistor, the first transistor comprising an oxide semiconductor film including a channel formation region;

a selection circuit comprising a first input terminal, a second input terminal, and an output terminal;

a first switch; and

a second switch, wherein the first input terminal of the selection circuit is electrically connected to the first switch and a first terminal of the first transistor, wherein the second input terminal of the selection circuit is electrically connected to the storage capacitor and a second terminal of the first transistor, and wherein the output terminal of the selection circuit is electrically connected to the second switch through the first memory circuit,

the driving method, in a high frequency operation mode, comprising the steps of;

turning the first switch ON, turning the first transistor OFF, turning the second switch OFF, and inputting a first data signal to the first memory circuit;

turning the first switch OFF, turning the first transistor ON, turning the second switch ON, and inputting the first data signal stored in the first memory circuit to the storage capacitor;

stopping application of a first power supply voltage to the storage device after inputting the first data signal to the storage capacitor;

resuming application of the first power supply voltage to the storage device; and

switching the selection circuit and inputting the first data signal stored in the storage capacitor to the first memory circuit and turning the second switch ON, and

the driving method, in a low frequency operation mode, comprising the steps of;

turning the first switch ON, turning the first transistor ON, turning the second switch OFF, and inputting a second data signal to the first memory circuit and the storage capacitor;

turning the first transistor OFF and stopping application of a second power supply voltage to the storage device after inputting the second data signal to the storage capacitor;

resuming application of the second power supply voltage to the storage device; and

switching the selection circuit and inputting the second data signal stored in the storage capacitor to the first memory circuit and turning the second switch ON.

19. The driving method according to claim 18,

wherein the first memory circuit comprises a first inverter and a second inverter,

wherein an output terminal of the first inverter is electrically connected to an input terminal of the second inverter, and

wherein an output terminal of the second inverter is electrically connected to an input terminal of the first inverter.

20. The driving method according to claim 18,

wherein at least one of the selection circuit and the first memory circuit comprises a second transistor, and

wherein the second transistor has higher field effect mobility than the first transistor.

21. The driving method according to claim 18,

wherein in a first case where the first switch is turned ON, the second switch is turned OFF, and

wherein in a second case where the first switch is turned OFF, the second switch is turned ON.

22. The driving method according to claim 18,

wherein the first memory circuit is configured to hold a data signal only in a period when a power supply voltage is supplied.

23. The driving method according to claim 18,

wherein the storage device further comprises:

a first node located between the first switch and the first terminal of the first transistor; and

a second node located between the storage capacitor and the second terminal of the first transistor,

wherein the first input terminal of the selection circuit is electrically connected to the first node, and

wherein the second input terminal of the selection circuit is electrically connected to the second node.

24. The driving method according to claim 18, wherein the second memory circuit is a nonvolatile memory circuit.

25. The driving method according to claim 24, wherein the first memory circuit is a volatile memory circuit.