Semiconductor memory having both volatile and non-volatile functionality and method of operating

• US 8,787,085 B2
• Filed: 05/28/2013
• Issued: 07/22/2014
• Est. Priority Date: 10/24/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US13/903,923
• Publication Number:
  US 20130250685A1
• Time in Patent Office: 420 Days
• Field of Search: 365/185.08, 365/185.17, 365/149, 365/150
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 : Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Claims

1. A semiconductor memory device comprising a string of memory cells connected in series, each said memory cell having:

a floating body region; and

a floating gate or trapping layer positioned above and insulated from said floating body region;

wherein said floating body region is configured to be charged to a level indicative of a state of said memory cell based on charge stored in said floating gate or trapping layer, upon restoration of power to said semiconductor memory device.

2. The semiconductor memory device of claim 1, wherein said memory device functions as volatile memory upon said restoration of power to said memory device.

3. The semiconductor memory device of claim 1, wherein said floating body region is configured to a predetermined state prior to being charged based on charge stored in said floating body or trapping layer.

4. The semiconductor memory device of claim 1, wherein said floating gate or trapping layer is configured to a predetermined state after said floating body region is charged to a level based on charge stored in said floating gate or trapping layer.

5. The semiconductor memory device of claim 1, further comprising a control gate positioned above said floating gate or trapping layer.

6. The semiconductor memory device of claim 1, further comprising a first region in electrical contact with said floating body region and a second region spaced apart from said first region and in electrical contact with said floating body region.

7. A semiconductor memory device comprising a string of memory cells connected in series, each said memory cell having:

a floating body region configured to be charged to a level indicative of a state of said memory cell to store the state as volatile memory;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as non-volatile memory indicative of said state of the memory cell; and

a control gate positioned above said floating gate or trapping layer,

wherein said charge stored in said floating body region determines a charge stored in said floating gate or trapping layer upon interruption of power to said semiconductor memory device.

8. The semiconductor memory device of claim 7, wherein said floating body region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said first region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said second region has said second conductivity type.

9. The semiconductor memory device of claim 7, wherein said transfer of data to said floating gate or trapping layer occurs in a non-algorithmic manner.

10. The semiconductor memory device of claim 7, wherein said transfer of data to said floating gate or trapping layer occurs upon interruption of power to said semiconductor memory device.

11. The semiconductor memory device of claim 10, wherein when power is restored to the device, data transfer from the floating gate or trapping layer to the floating body occurs in a non-algorithmic manner, and the device functions as volatile memory.

12. A semiconductor memory device comprising a string of memory cells connected in series, each said memory cell having:

a floating body region configured to be charged to a level indicative of a state of said memory cell to store the state as volatile memory;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; and

a control gate positioned above the floating gate or trapping layer,

wherein said state stored in said floating body region determines a current flowing through said semiconductor memory cell.

13. The semiconductor memory device of claim 12, wherein said floating body region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said first region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said second region has said second conductivity type.

14. The semiconductor memory device of claim 12, wherein said floating gate or trapping layer receives transfer of said data upon interruption of power to said semiconductor memory device.

15. The semiconductor memory device of claim 12, wherein said current flowing through said semiconductor memory cell determines the charge stored in said floating gate or trapping layer upon interruption of power to said semiconductor memory device.

16. The semiconductor memory device of claim 12, wherein said transfer of data to said floating gate or trapping layer occurs in a non-algorithmic manner.

17. The semiconductor memory device of claim 14, wherein when power is restored to said semiconductor memory device, data transfer from said floating gate or trapping layer to said floating body occurs in a non-algorithmic manner, and said semiconductor memory device functions as volatile memory.