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Memory device and signal processing circuit

  • US 8,787,102 B2
  • Filed: 05/17/2012
  • Issued: 07/22/2014
  • Est. Priority Date: 05/20/2011
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • a logic circuit configured to store data, the logic circuit including a first node and a second node;

    a first memory circuit electrically connected to the first node;

    a second memory circuit electrically connected to the second node; and

    a precharge circuit electrically connected to the first node, the second node, the first memory circuit, and the second memory circuit,wherein the first memory circuit comprises a first transistor and a first capacitor, and the second memory circuit comprises a second transistor and a second capacitor, each of the first transistor and the second transistor comprising an oxide semiconductor film having low off-state current,wherein the precharge circuit is configured to output a first precharge potential to the first node and a second precharge potential to the second node, andwherein off-state current density of the first transistor and the second transistor having the low off-state current is less than or equal to 100 zA/μ

    m.

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