Memory device and signal processing circuit
First Claim
1. A memory device comprising:
- a logic circuit configured to store data, the logic circuit including a first node and a second node;
a first memory circuit electrically connected to the first node;
a second memory circuit electrically connected to the second node; and
a precharge circuit electrically connected to the first node, the second node, the first memory circuit, and the second memory circuit,wherein the first memory circuit comprises a first transistor and a first capacitor, and the second memory circuit comprises a second transistor and a second capacitor, each of the first transistor and the second transistor comprising an oxide semiconductor film having low off-state current,wherein the precharge circuit is configured to output a first precharge potential to the first node and a second precharge potential to the second node, andwherein off-state current density of the first transistor and the second transistor having the low off-state current is less than or equal to 100 zA/μ
m.
1 Assignment
0 Petitions
Accused Products
Abstract
A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. A memory device includes a logic circuit including a first node and a second node, a first memory circuit connected to the first node, a second memory circuit connected to the second node, and a precharge circuit connected to the first node, the second node, the first memory circuit, and the second memory circuit. When reading data is performed, the precharge circuit outputs a precharge potential to the first node and the second node. The first memory circuit and the second memory circuit each include a transistor in which a channel is formed in an oxide semiconductor film.
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Citations
21 Claims
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1. A memory device comprising:
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a logic circuit configured to store data, the logic circuit including a first node and a second node; a first memory circuit electrically connected to the first node; a second memory circuit electrically connected to the second node; and a precharge circuit electrically connected to the first node, the second node, the first memory circuit, and the second memory circuit, wherein the first memory circuit comprises a first transistor and a first capacitor, and the second memory circuit comprises a second transistor and a second capacitor, each of the first transistor and the second transistor comprising an oxide semiconductor film having low off-state current, wherein the precharge circuit is configured to output a first precharge potential to the first node and a second precharge potential to the second node, and wherein off-state current density of the first transistor and the second transistor having the low off-state current is less than or equal to 100 zA/μ
m. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor device comprising:
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cells arranged in matrix of m rows and n columns, the cells each comprising; a logic circuit configured to store data, the logic circuit including a first node and a second node; a first circuit electrically connected to the first node; a second circuit electrically connected to the second node; and a precharge circuit electrically connected to the first node, the second node, the first circuit, and the second circuit, wherein the first circuit and the second circuit each include a transistor comprising an oxide semiconductor film having low off-state current and a capacitor, and wherein off-state current density of the transistor having the low off-state current is less than or equal to 100 zA/μ
m. - View Dependent Claims (17, 18)
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19. A memory device comprising:
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memory cells arranged in matrix of m rows and n columns, the memory cells each comprising; a logic circuit configured to store data, the logic circuit including a first node and a second node; a first memory circuit electrically connected to the first node; a second memory circuit electrically connected to the second node; and a precharge circuit electrically connected to the first node, the second node, the first memory circuit, and the second memory circuit, wherein the first memory circuit and the second memory circuit each include a transistor comprising an oxide semiconductor film having low off-state current and a capacitor, and wherein off-state current density of the transistor having the low off-state current is less than or equal to 100 zA/μ
m. - View Dependent Claims (20, 21)
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Specification