Structures for LUT-based arithmetic in PLDs
First Claim
1. A programmable logic device (PLD) including a plurality of logic array blocks (LAB'"'"'s) connected by a PLD routing architecture, wherein at least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages, the LE comprising:
- a K-input look-up table (LUT) (“
K-LUT”
), the K-LUT arranged to receive the plurality of binary input signals at respective inputs of the K-LUT and to provide, at a plurality of outputs of the K-LUT, respective binary result signals indicative of at least two stages of the plurality of stages of the arithmetic combination of the plurality of binary input signals;
an input line network including a network of input lines, the network of input lines arranged to receive a plurality of representative input signals from the PLD routing architecture that represent the plurality of binary input signals and to provide the plurality of binary input signals to the K-LUT, the input line network being configured to provide at least a first one of the plurality of binary input signals to both a first K-LUT portion and a second K-LUT portion in a first state, and provide a first carry-in signal to the first K-LUT portion and a second carry-in signal, which differs from the first carry-in signal, to the second K-LUT portion in a second state; and
an output line network including a network of output lines, the network of output lines arranged to receive, from the K-LUT, output signals that represent the binary result signals and to provide the network of output signals to the PLD routing architecture.
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Abstract
A programmable logic device (PLD) includes a plurality of logic array blocks (LAB'"'"'s) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT'"'"'s can perform arithmetic efficiently, as well as non-arithmetic functions.
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Citations
20 Claims
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1. A programmable logic device (PLD) including a plurality of logic array blocks (LAB'"'"'s) connected by a PLD routing architecture, wherein at least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages, the LE comprising:
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a K-input look-up table (LUT) (“
K-LUT”
), the K-LUT arranged to receive the plurality of binary input signals at respective inputs of the K-LUT and to provide, at a plurality of outputs of the K-LUT, respective binary result signals indicative of at least two stages of the plurality of stages of the arithmetic combination of the plurality of binary input signals;an input line network including a network of input lines, the network of input lines arranged to receive a plurality of representative input signals from the PLD routing architecture that represent the plurality of binary input signals and to provide the plurality of binary input signals to the K-LUT, the input line network being configured to provide at least a first one of the plurality of binary input signals to both a first K-LUT portion and a second K-LUT portion in a first state, and provide a first carry-in signal to the first K-LUT portion and a second carry-in signal, which differs from the first carry-in signal, to the second K-LUT portion in a second state; and an output line network including a network of output lines, the network of output lines arranged to receive, from the K-LUT, output signals that represent the binary result signals and to provide the network of output signals to the PLD routing architecture. - View Dependent Claims (2, 3, 4, 5)
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6. A programmable logic device (PLD) including a plurality of logic array blocks (LAB'"'"'s) connected by a PLD routing architecture, wherein at least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages, the LE comprising:
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a K-input look-up table (LUT) (“
K-LUT”
), the K-LUT arranged to receive the plurality of binary input signals at respective inputs of the K-LUT and to provide, at a plurality of outputs of the K-LUT, respective binary result signals indicative of the arithmetic combination of the plurality of binary input signals;an input line network including a network of input lines, the network of input lines arranged to receive a plurality of representative input signals from the PLD routing architecture that represent the plurality of binary input signals and to provide the plurality of binary input signals to the K-LUT, the input line network being arranged to provide at least a first one of the plurality of binary input signals to both a first K-LUT portion and a second K-LUT portion in a first state, and provide a first carry-in signal to the first K-LUT portion and a second carry-in signal, which differs from the first carry-in signal, to the second K-LUT portion in a second state; an output line network including a network of output lines, the network of output lines arranged to receive, from the K-LUT, a plurality of representative output signals that represent the binary result signals and to provide the plurality of representative output signals to the PLD routing architecture; and at least one output multiplexer, each of the at least one output multiplexers coupled to select among the respective binary result signals directly at the outputs of the K-LUT under the control of a carry-in signal to the LE, to provide an arithmetic output signal from the LE to an output line of the output line network. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A programmable logic device (PLD) including a plurality of logic array blocks (LAB'"'"'s) connected by a PLD routing architecture, wherein at least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages, the LE comprising:
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a K input look-up table (“
K-LUT”
), the K-LUT arranged to receive the plurality of binary input signals at respective inputs of the K-LUT and to provide, at a plurality of outputs of the K-LUT, respective binary result signals indicative of at least two stages of the plurality of stages of the arithmetic combination of plurality of binary input signals;an input line network including a network of input lines and an input multiplexer, the network of input lines arranged to receive a plurality of representative input signals from the PLD routing architecture that represent the plurality of binary input signals and to provide the plurality of binary input signals to the K-LUT, wherein the input multiplexer is configured to receive input signals from at least one of the network of input lines and provide output signals to the K-LUT, the input line network being configured to provide at least a first one of the plurality of binary input signals to both a first K-LUT portion and a second K-LUT portion in a first state, and provide a first carry-in signal to the first K-LUT portion and a second carry-in signal, which differs from the first carry-in signal, to the second K-LUT portion in a second state; and an output line network including a network of output lines and an output multiplexer, the network of output lines arranged to receive, from the K-LUT, output signals that represent the binary result signals and to provide the network of output signals to the PLD routing architecture, wherein the output multiplexer selects an output signal at outputs of the K-LUT. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification