Buffer control system and method for a memory system having outstanding read and write request buffers
First Claim
1. A memory controller for use with a system memory, the memory controller comprising:
- a flow control unit comprising;
a first buffer control circuit configured to determine a number of outstanding memory requests of a first kind issued to the system memory; and
a second buffer control circuit configured to determine a number of outstanding memory requests of a second kind issued to the system memory,wherein the flow control unit is configured to provide a flow control signal to control further issuance of memory requests of the first and second kinds to the system memory based on the numbers of outstanding memory requests of the first and second kinds, respectively, including enabling issuance of additional memory requests of the first kind to the system memory when the number of outstanding memory requests of the first kind is within a range and halting issuance of additional memory requests of the first kind when the number of outstanding memory requests of the first kind is outside of the range.
7 Assignments
0 Petitions
Accused Products
Abstract
A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write requests to the system memory is separately controlled based on the number of outstanding read and write requests, respectively. For example, the issuance of read and write requests can be managed by halting and resuming the issuance of read and write requests to the system memory to maintain the number of outstanding read requests between first and second read thresholds and to maintain the number of outstanding write requests between first and second write thresholds, respectively.
337 Citations
20 Claims
-
1. A memory controller for use with a system memory, the memory controller comprising:
-
a flow control unit comprising; a first buffer control circuit configured to determine a number of outstanding memory requests of a first kind issued to the system memory; and a second buffer control circuit configured to determine a number of outstanding memory requests of a second kind issued to the system memory, wherein the flow control unit is configured to provide a flow control signal to control further issuance of memory requests of the first and second kinds to the system memory based on the numbers of outstanding memory requests of the first and second kinds, respectively, including enabling issuance of additional memory requests of the first kind to the system memory when the number of outstanding memory requests of the first kind is within a range and halting issuance of additional memory requests of the first kind when the number of outstanding memory requests of the first kind is outside of the range. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. An apparatus, comprising:
a controller configured to determine a number of outstanding memory requests of a first type issued to a memory and determine a number of outstanding memory requests of a second type issued to the memory, the controller further configured to control issuance of memory requests of the first type to the memory based, at least in part, on the number of outstanding memory requests of the first type and to control issuance of memory requests of the second type to the memory based, at least in part, on the number of outstanding memory requests of the second type. - View Dependent Claims (9, 10, 11, 12, 13)
-
14. An apparatus, comprising:
-
a request queue configured to receive memory requests of a first type and memory requests of a second type, the request queue configured to selectively provide the memory requests of the first type according to a first flow control signal and to selectively provide the memory requests of the second type according to a second flow control signal; and a flow control unit configured to determine a number of outstanding memory requests of the first type and to determine a number of outstanding memory requests of the second type, the flow control unit further configured to provide the first flow control signal and the second flow control signal, the first flow control signal based, at least in part, on the number of outstanding memory requests of the first type and the second flow control signal based, at least in part, on the number of outstanding memory requests of the second type. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification